A live examination of China's AI industry after three years of gear-shifting. The logic of competition has migrated from "chip specs" to "system efficiency," from "model capabilities" to "industrial deployment," and from "process-node catch-up" to "architecture innovation." Now in its eighth year, WAIC felt less like a tech expo and more like an industrial delivery floor.
I. Three Gear Shifts in Eight Years
WAIC has been running for eight years. Exhibition space grew from 52,000 m² to 100,000 m²; participating companies expanded from 500+ to 1,100+. Doubling the numbers is the easy part—the harder part is the shift in focus.
At the 2024 show, exhibitors crowded around booths competing over who had the bigger parameter count or the longer context window. The core mandate was to prove to the outside world: "we too have a competitive foundation model." The evaluation framework was still stuck on "benchmarking against GPT-4": parameter count, token length, leaderboard rankings. The model itself was the protagonist; applications were accessories.
In 2025, the spotlight shifted to Agent frameworks and embodied intelligence prototypes. The industry began figuring out how to "package" model capabilities into specific tasks. The Agent concept was hot, but most demonstrations were still demo-grade—they could show one task flow but couldn't guarantee stable daily operation. Humanoid robots started appearing in density, but what they did was backflips and parkour.
By 2026, every exhibitor brought products that could run end-to-end in real-world scenarios. Even mass-production delivery numbers were put on the table. One exhibiting company executive put it bluntly: "Nobody is showing off benchmark scores anymore. Every vendor's moves point in the same direction—AI is finally stepping out of the screen and into real-world scenarios."
What is the underlying driver of this shift? The four deep-dive observations below will build the case, but here is the thesis statement first: compute infrastructure maturity has crossed a tipping point. Supernodes pushed system-level compute utilization from 30–45% to 70–85% (derivation in Observation 1). Domestic chips crossed from "inference only" to "can train trillion-parameter models" (derivation in Observation 2). New-architecture chips bypassed the dual bottlenecks of process node and HBM (derivation in Observation 3). When the underlying compute supply is no longer the core contradiction, industrial attention shifts upward: how to turn compute into productivity.
Key numbers from this WAIC: 1,100+ exhibitors, 3,000+ exhibits, 300+ global debuts. The intelligent computing and embodied intelligence tracks each drew 200+ companies, together accounting for more than a third of all exhibitors. Nine Turing Award and Nobel Prize laureates attended; Andrew Yao (Yao Qizhi) chaired the inaugural WAIC Academic conference with 284 global paper submissions. ¥16.2 billion in intent-to-collaborate agreements were signed.
Shanghai announced policy targets: by the end of the 15th Five-Year Plan, deploy 100,000 humanoid robots into factories and achieve 80%+ smart-agent adoption among industrial enterprises above designated size. In 2025, China's AI core industry exceeded ¥1.2 trillion in scale, with AI penetration in key industries surpassing 80%; 2026 is expected to maintain 30%+ growth.
At the opening ceremony, the World Artificial Intelligence Cooperation Organization was announced—China-led, responding to "Global South" calls. The National Development and Reform Commission released an AI Cooperation Development Action Plan, and the Ministry of Industry and Information Technology guided the release of an International AI Ethics Governance Action Plan. Institutional supply is beginning to keep pace with industry rhythm.
But more important than the numbers and policies is this: the logic of competition has changed. What follows is a broad scan, then four deep dives on the most consequential threads.
II. Broad Scan
Compute: Supernodes Replace Single Chips as the Unit of Competition
If you look at only one trend, it's "supernodes." Among WAIC 2026's Top 10 Signature Innovations, every compute-related honoree was a supernode product. The granularity of industrial competition has risen from "single chip" to "system-level coordination efficiency."
What is a supernode? Per the CAICT (China Academy of Information and Communications Technology) Supernode Development Report: a system supporting 32+ AI chips interconnected via high-speed links into a logically unified compute pool, with chip-to-switch bandwidth ≥ 400 GB/s, switch latency < 500 ns, and intra-domain unified memory addressing.
Four signature-level supernodes shared the stage:
Huawei Ascend Atlas 950 SuperPoD—first public live hardware showing. On-site: 1,024 Ascend cards, scalable to 8,192. At full 8,192-card configuration, the scale is approximately 56× Nvidia's NVL144 (144 cards); the on-site 1,024-card configuration is about 7× NVL144. Delivers 1 EFLOPS FP8 / 2 EFLOPS FP4 compute, 256 TB global unified memory address space, with the Lingqu 2.0 interconnect protocol achieving 3 μs RTT latency. Huawei claims total compute leadership over Nvidia's NVL576 (expected to ship in 2027)—specific multiples await verification once that product launches.
Sugon 8000 "Dengfeng" (Summit)—fully domestic 100,000-card AI super-cluster, a "super-intelligence fusion" technical approach, covering FP64 down to INT8 full precision. 300+ application optimizations completed; 70+ applications scaled to 10,000-card level. Integrated into the National Supercomputing Internet.
ZTE OEX Supernode—open and decoupled approach, pioneering orthogonal backplane-free zero-cable design. Partnering with Biren/Metax/Enflame/Iluvatar CoreX to build the Matrix supernode. Shortlisted for the SAIL Award Top 30.
Alibaba Zhenwu M890 × Panjiu AL128—full chain from chip to server to Qwen Cloud; the Bailian platform serves 5 million users.
H3C UniPoD S80000—covering a full product line from 32 to 1,024 cards, scalable up to 16,384 cards. Training performance up 70%, inference performance up 3×. Design philosophy: "single rack = intelligent computing cluster." Entire-rack liquid cooling coverage at 75–80%, max thermal density 120 kW. Multi-vendor GPU compatible. Already deployed in cluster configurations across multiple large-scale intelligent computing projects.
Huawei also exhibited the Atlas 850E air-cooled supernode—deployable in traditional data centers without liquid-cooling retrofits. 96-card expansion, sub-10ms inference latency, native support for FP8/mxFP8/HiF8/INT8/mxFP4 low-precision formats, paired with 4.0 TB/s high-speed memory bandwidth. The significance: supernode technology is no longer exclusive to greenfield data centers—legacy air-cooled facilities can use it too.
Domestic GPU vendors also assembled in full force at the Zhangjiang exhibition area. Over a dozen general-purpose high-compute chip companies shared the stage with 67 domestic debuts. Dongfang Suanxin (Oriental Compute), Moore Threads, Metax, Iluvatar CoreX, Enflame, Kunlunxin—nearly the full roster. The biggest difference from last year: in 2025 they competed on single-card specs; this year every one of them pitched system-level solutions and deployment cases.
Embodied Intelligence: The Acceptance Standard Changed
200+ robotics companies, 300+ robots performing live dynamic demonstrations—Hall H3 was the most eye-catching area at WAIC. But the most critical shift wasn't in quantity; it was in the evaluation standard.
Nobody was showing off backflips and parkour anymore. The universal acceptance criterion on the floor was: can it work a full 8-hour shift on a real production line?
AgiBot (Zhiyuan) Expedition A3 Ultra was named the only robotics product selected as a Signature Innovation. 174 cm human-proportioned body, 360° vision + LiDAR fusion perception, UWB + RTK centimeter-level positioning, auto-charging + quad-layer safety system. Positioned for exhibition hall guiding, hotel reception, and retail storefront service.
Ant Lingbo's robotic smart pharmacy: 3 robots of different configurations, all running the LingBot-VLA cross-embodiment foundation model, collaboratively completing the full workflow of consultation → purchasing → prescription → dispensing → packaging, closed-loop within 90 seconds.
Fourier GR-3 performing autonomous task loops in home scenarios—from "grab the apple" to "find the plushie" long-sequence tasks. Simultaneously launched the GRW wheeled assistive robot for elderly care.
Elite Robotics Centaur-G1 wheeled humanoid: dual-arm repeat positioning accuracy of ±0.1 mm, already deployed on the production line of a major optical communications company, from precision assembly to packaging and testing.
Keenon demonstrated a VLA-architecture service robot integrated with a world model, covering retail/café/hotel new scenarios.
In 2026, China's humanoid robot annual production volume is expected to exceed 100,000 units.
AI Agents: The Terminal Revolution
AI Agents are the nervous system connecting compute and robotics. At WAIC 2026, the core narrative around agents was "terminal revolution."
Baidu "Daizi" (Buddy)—Signature Innovation. A general-purpose agent that autonomously understands, decomposes steps, and invokes tools after receiving tasks in natural language. Handles file processing, web operations, data analysis, report writing, PPT creation. Positioning upgraded from "answering questions" to "completing work."
StepFun Agent OS + StepX Neo—Signature Innovation. Moves agent capabilities from individual apps to the operating system layer, enabling multi-terminal coordination across phones, industrial equipment, and even robots.
Nubia × ByteDance Doubao—world's first AI agent phone. Autonomously reads screen content and simulates touch controls, automating food ordering and payment across 200+ apps.
Honor × Alibaba—collaborating on next-generation terminal OS "Agentic OS"; world's first "Robot Phone" debuted.
Siemens Eigen—world's first industrial automation engineering AI agent. From engineering planning, writing control software, system configuration to optimization and commissioning—end-to-end without human intervention.
Kaos—launched an industrial world model, "loading" real factories into AI. Through ontological modeling and digital twins, AI understands how every piece of equipment operates.
Foundation Models & AI4Science
MiniMax showcased its next-generation flagship model M3 across its full product matrix. SenseTime released SenseNova-U1 Pro, benchmarking against GPT-Image-2, with native 8K resolution output. Baidu launched the "Xinyun Moti" full-stack AI product matrix.
Alibaba Qwen delivered the most notable commercial signal: a "peak-off-peak Token" pricing model. Users get up to 80% off (2-zhe, i.e., 20% of standard price) for tokens used between 10 PM and 8 AM. This signals that the supply side has begun differentiating marginal costs—similar to peak/off-peak pricing in electricity markets.
In AI4Science, Tianwu Tech's Xiao-Wu™ protein design platform was named a Signature Innovation, compressing 2–5 year R&D cycles to 2–6 months, reducing experimental samples from 10,000+ to 100, and boosting success rates from 1% to 30%. XtalPi has "evolved" from its 2023 Signature Innovation into an AI autonomous discovery system, compatible with external domain-specific models, achieving full-pipeline unmanned closed-loop operation. Insilico Medicine advanced the world's first AI-discovered innovative drug into Phase III clinical trials.
III. Deep Dive
Observation 1: Supernodes—The Real Variable in the Token Cost Curve?
What Problem Do Supernodes Solve?
The pain point of traditional AI clusters isn't insufficient single-chip compute. It's that as chip count grows, communication overhead grows even faster, and actual compute utilization falls off a cliff.
To understand this, we need to trace how data actually flows during inference or training.
Consider large-scale MoE model training. When you connect thousands of GPUs via InfiniBand or RoCE networks, data exchange between cards traverses a long physical path: compute chip → on-chip cache → HBM → PCIe bus → NIC → optical module → fiber → switch → fiber → optical module → NIC → PCIe bus → HBM → on-chip cache → peer compute chip. Every hop introduces latency and bandwidth loss. The larger the cluster, the higher the proportion of total time consumed by All-to-All (all-to-all communication, where every node exchanges data with every other node). In MoE model training, All-to-All communication can account for 40–60% of total time.
This means: a theoretically 10,000-card cluster should have 10,000× single-card compute, but effective compute may only be at the 3,000–4,500-card level. Compute utilization: 30–45%.
The supernode solution isn't to boost single-chip performance—it's to change the physical path of inter-chip communication. Instead of hundreds to thousands of chips communicating through the long PCIe → NIC → switch → NIC → PCIe chain, a dedicated high-speed bus enables direct point-to-point interconnection between any two chips via the UnifiedBus protocol. Cross-node communication drops from the "network" level to the "bus" level—latency goes from microseconds to nanoseconds, and bandwidth increases by an order of magnitude.
Why Inference Also Gets a 3× Boost
Huawei's published data: the Ascend supernode achieves 3× single-card performance improvement over traditional servers in low-latency inference scenarios. The training-side communication bottleneck is straightforward to understand, but why does inference also see a 3× gain?
Inference and training have different communication patterns, but the bottleneck similarly lies in data movement. Specifically:
First, the workload characteristics of Agentic inference have changed. A traditional single-shot query (e.g., "translate this text") requires only one forward pass—communication overhead is negligible. But Agent inference is a combination of multi-turn dialogue + long context + frequent tool calls. A single Agent task may involve 20–50 rounds of dialogue, each requiring all prior conversation history as context fed to the model. This means KV Cache read volume grows linearly with turn count. When KV Cache exceeds single-card memory capacity, cross-card reads are needed—and inter-card bandwidth becomes the bottleneck.
The supernode's unified memory addressing plays a critical role here. In a traditional cluster, each card's HBM is independent; cross-card KV Cache reads must traverse the network. The supernode's 256 TB unified memory space lets all cards' memory form a logical pool—the Agent's long conversation context doesn't need to be shuttled between cards but is read and written directly within the unified address space. The Atlas 850E product description confirms this logic: it specifically mentions "matching Agent multi-turn dialogue, high-frequency KV cache read-write workloads" and "support for million-token-level ultra-long context."
Second, MoE model inference inherently requires All-to-All communication. When inferring a MoE model, each token must be routed to the card hosting the correct expert, computed, then routed back. This All-to-All communication pattern is identical to training, just at lower throughput. Lingqu 2.0 compresses single-hop communication latency from 2 microseconds to 200 nanoseconds; across an Agent's many inference rounds, the cumulative communication time savings become substantial.
Third, tensor parallelism efficiency for concurrent inference improves. Large-model inference typically uses Tensor Parallelism—splitting a single matrix multiplication across multiple cards and then aggregating results. In traditional clusters, the aggregation step traverses the PCIe → network → PCIe path, incurring high latency. In a supernode, aggregation completes directly over the high-speed bus—latency drops by an order of magnitude. For 70B+ model inference, tensor parallelism communication overhead accounts for 15–25% of total time; once reduced to nanosecond level, this overhead becomes nearly negligible.
This is why the 3× improvement holds for inference: not because the chips got faster, but because the physical path for data movement was compressed. The Ascend chip itself hasn't changed—what changed is how data moves between cards.
Technical Breakdown of Lingqu 2.0
Lingqu 2.0 is Huawei's proprietary interconnect protocol. What exactly does it do?
- Communication bandwidth: 15× improvement over traditional interconnect protocols. In traditional clusters, inter-chip communication goes through PCIe 5.0 at approximately 128 GB/s. Lingqu 2.0 achieves all-to-all direct connection via a full-optical Mesh topology, with single-chip interconnect bandwidth at the TB/s level.
- Communication latency: single-hop reduced from 2 μs to 200 ns—a 10× reduction. In traditional clusters, a single cross-node communication RTT (round-trip time) is approximately 5–10 μs (including NIC processing + optical module + switch forwarding). Lingqu 2.0 uses circuit-level direct connection (bypassing the network protocol stack) to push RTT below 3 μs.
- Unified memory addressing: 256 TB global address space. In traditional clusters, each card's HBM is independently addressed; cross-card access requires RDMA or MPI. Lingqu 2.0 enables all NPUs to share the same address space at the hardware level—a read/write request from one card can directly access any other card's memory without OS involvement.
Taken together, these three advances essentially turn "network communication" into "bus access." At the software level, a cross-card read no longer needs to traverse the TCP/IP stack (or RDMA's verbs API)—it becomes a regular memory load instruction. A 1–2 order-of-magnitude latency reduction is dictated by physics.
Under What Conditions Does "85%+ Utilization" Hold?
"System-level compute utilization pushed from 30–45% to 85%+"—this figure comes from East Money's (Dongfang Caifu) July 2026 analysis of Huawei technical documentation. The conditions for this claim deserve scrutiny:
Optimistic case: For large-scale MoE model training (the design-target scenario for supernodes), All-to-All communication accounts for 40–60% of total time. After Lingqu 2.0 reduces communication latency by 10×, communication overhead compresses from 40–60% to 5–15%, and the effective compute time share rises from 40–60% to 85–95%. This derivation is theoretically sound.
Cases requiring a discount:
- Mixed workloads: In production, clusters don't run just one model type. Mixed scheduling of training + inference + data preprocessing introduces additional resource-switching overhead.
- Failures and degradation: In a 10,000-card cluster, cards fail every day. Fault isolation, checkpoint recovery, and degraded operation all eat into effective compute time. The Ascend 384 supernode's 750-unit commercial deployment experience is relevant here—it suggests the engineering has cleared the failure-rate curve's break-in period.
- Model fit: Not all model architectures can fully exploit the supernode's interconnect advantages. Dense models' AllReduce communication pattern depends more on collective communication tree topologies than MoE's All-to-All; Lingqu 2.0's all-peer direct connection may not yield proportional improvements.
Reasonable expectation: Under mixed production workloads, effective utilization may run 10–15 percentage points below the theoretical value—in the 70–80% range. This still nearly doubles the 30–45% of traditional clusters. The improvement remains substantial, but 85%+ is not a guaranteed floor.
ZTE's Differentiation: Open Decoupling + Zero Cable
ZTE's OEX supernode takes a different path. Core innovations:
Orthogonal backplane-free zero-cable design—in traditional high-density server racks, compute trays are interconnected through thousands of copper cables on the backplane. These cables cause three problems: physical space consumption, signal integrity degradation (high-frequency signals attenuate severely through copper), and assembly yield issues. OEX uses an orthogonal architecture where compute trays and switch trays intersect perpendicularly and connect physically through precision contact connectors—no cables whatsoever.
ZTE claims interconnect cost reduced by 80%. Is this magnitude reasonable? A rough breakdown: traditional rack interconnect costs comprise four components—cable materials (~15%), connectors (~25%), assembly labor and testing (~20%), and signal compensation chips/redrivers (~40%, because copper cable attenuation requires additional signal conditioning). The zero-cable design eliminates most of the first three components, but the fourth (signal compensation) is partially retained in the orthogonal architecture. So "80% reduction" roughly means: eliminating approximately 4/5 of traditional cable-related overhead while retaining some necessary signal conditioning cost. The magnitude is credible but requires validation from actual product deployments.
Open decoupling—not locked to a single chip vendor. Partnering with 5 domestic GPU companies (Biren, Metax, Enflame, Iluvatar CoreX) to build the Matrix supernode. Starting from 32–128 cards per rack, scaling to 100,000-card elasticity through multi-PoD heterogeneous mixing.
The significance of this approach: Huawei's supernode is a closed ecosystem (Ascend-exclusive); ZTE's is open (multi-chip coordination). If supernodes are to be deployed at scale across national intelligent computing centers, they can't all come from one vendor. ZTE's solution provides an alternative, and its deployment threshold for legacy data center retrofits is lower.
H3C UniPoD S80000: The Third Path—Full-Stack Synergy
Beyond ZTE, H3C's (New H3C Group) UniPoD S80000 supernode deserves separate treatment.
H3C takes a third path distinct from both Huawei and ZTE: it doesn't manufacture its own chips. Instead, it focuses on six-layer full-stack synergy across "compute–network–storage–cloud–security–O&M." The core thesis: supernode efficiency comes not just from interconnect architecture but from systemic optimization across computing, networking, storage, cloud platform, security, and operations. Official data claims full-chain TCO reduction of 30%+ and energy cost reduction of 40%+.
Product specs: 32 to 1,024 cards across the full product line, scalable to 16,384 cards. Training performance up 70%, inference performance up 3×. Liquid cooling coverage at 75–80% of the rack, max thermal density 120 kW. Scale-up architecture enables intra-rack GPU full-mesh interconnect, with multi-vendor GPU compatibility.
H3C's differentiation in three points:
First, multi-vendor GPU compatibility. Similar to ZTE's open decoupling, H3C doesn't lock customers into a single chip vendor. But the distinction is that ZTE's Matrix supernode is built primarily with domestic GPU partners (5 Chinese chip companies), while H3C's compatibility strategy is broader—including forward compatibility with next-generation high-performance AI accelerators regardless of vendor origin. This is more attractive for customers who already operate mixed-chip clusters.
Second, network-layer advantage. H3C is one of China's highest-market-share Ethernet switch vendors, showcasing a full series of single-chip 102.4T intelligent computing switches. High-speed interconnect within supernodes doesn't rely solely on dedicated buses—it also requires high-performance Ethernet for Scale-out layer expansion. H3C's network design expertise is its moat.
Third, full-stack TCO optimization rather than single-point performance breakthrough. Huawei competes on system-level compute utilization (pushing from 30–45% to 70–85%). ZTE competes on interconnect cost (80% reduction). H3C competes on full-chain TCO (30%+ reduction). The three dimensions of optimization don't fully overlap—which means the supernode value space is wider than commonly assumed.
Industry Value Chain—How BOM Costs Break Down
East Money's analysis puts the BOM cost of an 8,192-card complete supernode at approximately ¥440 million. Where does this number come from? A rough reverse-engineering:
Assume the cost per Ascend 950DT accelerator card (including HBM/packaging/cooling) is in the ¥30,000–40,000 range (domestic chip manufacturing cost structures are typically lower than Nvidia's, but HBM remains a major cost item). 8,192 cards = ¥250–330 million. Racks and liquid cooling systems: 16 compute cabinets, each with cold plates, CDUs (Coolant Distribution Units), piping, and quick-disconnect fittings—approximately ¥3–5 million per cabinet = ¥50–80 million. High-speed switching equipment and optical modules: supernode internal switching is 5–10× denser than traditional clusters—approximately ¥50–60 million. Connectors, PCBs, power supplies, cables, etc.: approximately ¥30–50 million.
Total: ¥350–520 million, with a midpoint around ¥430 million—broadly consistent with East Money's ¥440 million figure.
The significance of this breakdown lies not in the precise number but in how the value distribution is shifting. In traditional GPU servers, GPU cards account for 70–80% of cost. In supernodes, the GPU card share drops to 60–70%, while high-speed switching, liquid cooling, and connectors rise from under 10% to 25–30%. In the supernode era, the profit pool for compute infrastructure is diffusing from chips toward interconnects and thermal management.
This is also why Huawei partnered with 20+ companies to launch China's first NPO (Near-Packaged Optics) optical interconnect MSA (Multi-Source Agreement). The supernode value chain is more complex than the single-chip era—it's not something one company can complete alone.
The "Token at Cabbage Prices" Hype Needs Cooling
Media reports claiming "Token prices will hit cabbage levels within a year or two" are overly optimistic. To derive the true trajectory of Token prices, we first need to decompose Token marginal cost structure:
Token marginal cost ≈ Compute depreciation + Model training amortization + Inference framework efficiency + Operations + Data + Bandwidth
Item-by-item analysis of how supernodes and other advances affect each component:
- Compute depreciation (hardware cost of the inference cluster allocated per token): The supernode's 3× single-card efficiency directly compresses this to 1/3 of its previous level. This is the most heavily impacted component. But the premise is that supernode procurement cost doesn't rise proportionally: if a ¥440 million supernode costs 3× a traditional cluster, the per-token depreciation savings evaporate.
- Model training amortization (training cost allocated to each inference call): Declining domestic chip training costs indirectly pressure this component. But training is a one-time investment; once a model matures, this component becomes negligible in marginal cost (large training costs are amortized across massive inference volumes).
- Inference framework efficiency: Continuous optimization of frameworks like vLLM and TensorRT-LLM (PagedAttention, Speculative Decoding, etc.) improves efficiency independently of hardware. This component sees roughly 20–30% annual improvement.
- Operations: Larger clusters mean more complex operations; supernode O&M costs aren't necessarily lower than traditional clusters. Full liquid-cooling maintenance requirements exceed air-cooled systems.
- Data: The cost of data collection, cleaning, and labeling is unaffected by hardware advances.
- Bandwidth: If inference is deployed at edge nodes, bandwidth cost is negligible. For centralized deployments serving national users, bandwidth remains a factor.
Overall, compute depreciation is the largest single component of Token marginal cost. Based on public API pricing from major providers: for a GPT-4o-class model, output pricing is approximately $15 per million tokens. Of this, compute depreciation (GPU procurement + electricity + data center depreciation allocated per inference) accounts for approximately 40–55%, model training amortization 10–15%, inference framework + operations 15–20%, data + bandwidth + other 15–25%. This breakdown is estimated from public API pricing and GPU TCO models; actual figures vary by provider.
So Token prices have room to decline over 18–24 months—but not to "cabbage levels." A more reasonable estimate: Token prices for equivalent-quality inference decline 40–60%, and factoring in the compounding effect of inference framework optimization, the total decline could reach 50–70%.
The more likely trend is Token pricing stratification. Peak-hour high-quality inference (Agent multi-turn dialogue, long context, high concurrency) commands premium pricing. Off-peak batch inference (log analysis, content moderation) goes for cabbage prices. Alibaba's peak/off-peak Token pricing at 80% off is the primitive form of stratified pricing.
The signal worth tracking: Q4 Atlas 950 first-deployment inference performance data and pricing models.
Observation 2: Domestic Chip Training—"0 to 1" Is Done; "1 to 10" Has Just Begun
Three Milestones
Milestone 1: Meituan LongCat-2.0 (open-sourced June 30)
This is currently the hardest piece of evidence.
- 1.6 trillion parameter MoE architecture; average activation per token: approximately 48 billion parameters
- Pre-trained on 50,000+ domestic compute chips, using 35+ trillion tokens
- Used a mainstream domestic chip that entered mass production in H2 2023—not the latest model
- "From the first token to the last token, everything ran entirely on domestic compute"—no GPU pre-trained weights used for initialization
- Performance on Coding/Agent benchmarks approaches Anthropic Opus 4.6 (released February 2026)
The significance of this milestone lies not in model performance per se (Opus 4.6 is no longer the strongest benchmark), but in this: it used engineering practice to overturn the industry consensus that "domestic chips can't train trillion-parameter models."
In late 2025, the consensus among model startup CTOs was: "Training on domestic chips takes at least 150% longer than GPUs, with 2×+ higher costs. We don't recommend using domestic chips for training." The prevailing practice was to pre-train on H100/H800 first, then reproduce on domestic compute.
LongCat-2.0 trained a trillion-parameter model on 2023 "old chips," shattering this perception outright.
Milestone 2: Moore Threads MoE-236B (WAIC debut)
Moore Threads showcased the complete training of a MoE-236B foundation model from scratch, along with the world's first 5D world model "Peking University EvoPhys-World" with full-stack native training.
Using the S5000 GPU (mass-produced in 2025). Currently, a 10,000-card cluster is training trillion-parameter models for commercial customers. Moore Threads developed its own MUSA (Meta Unified System Architecture) full-stack software-hardware technology—from hardware architecture, instruction set, and drivers to compilers, foundational software libraries, and development tools.
Milestone 3: Industry Perception Inversion
Omdia analyst Zhan Molei's assessment: "The case of training large models on a 10,000-card cluster marks the completion of domestic AI chips' '0 to 1' crossing on the training side—trillion-parameter MoE model full-pipeline pre-training has been proven engineering-feasible. The essence of this breakthrough is not catching up on chip hardware specs, but rather a system-level achievement of years of co-evolution among 'model architecture–engineering implementation–chip capability.'"
Why the Breakthrough Happened Now and Not Earlier
The answer to this question matters more than the milestones themselves.
First, the popularization of MoE architecture changed the hardware demand structure on the training side.
To understand this, we need to compare the communication patterns of Dense models versus MoE models.
In traditional Dense model training, all parameters participate in every forward pass. Gradient updates require AllReduce across all cards—each card sends its gradients to all others, then averages. The data volume for this operation = model parameter count × 4 bytes (FP32 gradients). For a 175B Dense model, each gradient sync requires transmitting 700 GB of data. In a 10,000-card cluster, AllReduce completes through ring or tree topologies; communication time scales with log(N) × model size. The larger the cluster, the slower the communication.
MoE model communication patterns are completely different. Each forward pass activates only a subset of experts (e.g., LongCat-2.0's 1.6 trillion parameters activate only 48 billion per token). Activated tokens must be routed to the cards hosting the correct experts. This operation is called All-to-All: each token is sent to its corresponding expert, computed, then sent back. MoE's All-to-All communication volume doesn't equal batch_size × hidden_dim × 2; it also depends on expert routing patterns: each token selects top-k experts per layer (k typically 2–8), with communication volume approximately batch_size × hidden_dim × top_k × 2. But the key characteristic holds: communication volume is independent of total model parameter count—it scales only with activation size.
This means: MoE architecture transformed the communication bottleneck from "how big the model is" to "how many tokens are processed at once." Larger batch sizes mean more communication, but communication overhead can be amortized by increasing batch size (better compute-to-communication ratio). Domestic chips' weakness (lower single-card interconnect bandwidth versus Nvidia) was partially circumvented by this architectural trend.
Second, engineering accumulation from the inference side fed back into training.
Domestic chips have been deployed heavily for inference since 2023. Inference and training share many foundational components: operator libraries (GPU implementations of matrix multiplication, attention, normalization), collective communication libraries (domestic alternatives to NCCL), and graph compilers (mapping high-level model descriptions to hardware execution).
In inference scenarios, engineering teams must perform operator-level optimization for each model architecture—pushing GEMM (General Matrix Multiply) to theoretical peak, optimizing Attention memory access patterns to the limit, and tuning KV Cache storage formats for minimal bandwidth. These optimization experiences transfer directly to the training side—training simply adds backward propagation and gradient synchronization on top of inference.
Over two-plus years of intensive inference deployment, domestic chip vendors accumulated extensive experience in operator library coverage and optimization depth. Once this experience crossed the threshold of "covering 95%+ of common model architectures," training-side adaptation shifted from "tuning from scratch for every new model" to "composing existing operators."
Third, software stack maturity crossed an inflection point.
Meituan trained a trillion-parameter model on 2023 chips—not because of chip performance advances (those 2023 chips had long existed), but because of continuous software stack optimization over the ensuing two years. Specifically:
Distributed training frameworks must solve four problems: data parallelism (distributing different data batches across cards), tensor parallelism (splitting a large matrix across cards), pipeline parallelism (distributing different model layers across cards), and expert parallelism (MoE-specific, distributing different experts across cards). Each parallelism dimension requires corresponding communication primitives and scheduling strategies.
By end-2025, mainstream domestic chip distributed training frameworks supported free combinations of all four parallelism modes—3D parallelism + expert parallelism as a 4D training strategy was running. Meituan's technical report implies a key piece of information: LongCat-2.0's training wasn't completed on the latest chips, but on two-year-old hardware—this means the bottleneck was never the chip itself, but software stack maturity. Once the software stack crossed the tipping point, old chips could also train trillion-parameter models.
Fourth, international sanctions forced the ecosystem into closure.
When access to H100/H800 became uncertain or impossible, companies had no choice but to invest their best engineering talent into domestic chip adaptation. This "forced investment" began paying off two years later. Without sanctions, under natural market selection, the domestic chip training ecosystem might have taken another three to five years—because training on GPUs was faster and easier, with no reason to invest heavily in domestic chip adaptation and optimization.
From "Training Feasible" to "Training Economical"—How Far?
"Training feasible" and "training economical" are two different problems. Feasible means "can run"; economical means "is more cost-effective than GPUs."
To judge when domestic chip training costs can truly reach GPU parity, several variables need monitoring:
Variable 1: MFU (Model FLOPs Utilization). Training efficiency depends on MFU—effective compute time as a fraction of total time. Nvidia H100 clusters training MoE models achieve MFU in the 45–55% range (from public data). Domestic chip MFU figures aren't publicly available, but based on inference-side experience, they're estimated at 30–45%—meaning training the same-scale model on domestic chips takes 20–50% longer. If MFU can improve from 35% to 45% (reaching GPU parity) within 12 months, training costs can break even.
Variable 2: Chip procurement cost. Domestic AI chips typically have lower per-card costs than Nvidia (mature process + no HBM dependency in some cases), but total cluster cost must account for interconnect, cooling, and operations. If supernode deployment can scale within 12 months, system-level TCO (Total Cost of Ownership) has a chance to match or undercut GPU clusters.
Variable 3: Engineering team experience curve. Domestic chip training adaptation experience has accumulated for approximately 2 years; Nvidia's CUDA ecosystem has accumulated over 10 years. But the experience curve is steeper in the early phase—the time from "can't use" to "can use" is far shorter than from "can use" to "expert." Domestic chips are currently in the transition from "can use" to "expert," where efficiency gains are fastest.
Synthesizing all three variables, the time window for "training cost reaching GPU parity" is approximately 12–18 months. If MFU improvement is slower than expected (e.g., bottlenecks in adapting certain model architectures), it could extend to 18–24 months. If supernodes + new-architecture chips (e.g., Dongfang Suanxin) scale faster than expected, it could compress to within 12 months.
Gaps that deserve clear-eyed assessment:
- LongCat-2.0 approaches Opus 4.6, but Opus 4.6 itself is no longer the strongest benchmark. Models trained on domestic chips still have roughly a one-generation gap in absolute performance.
- Moore Threads' MoE-236B is far smaller in scale than LongCat's 1.6 trillion. Going from 236B to trillion-level still poses engineering challenges.
- Training stability at 10,000+ card clusters—particularly hardware failure rates and checkpoint recovery efficiency during long runs—currently lacks publicly detailed data. Nvidia has over a decade of engineering accumulation here.
Observation 3: Dongfang Suanxin DF1000—The Third Path Around Process Nodes
Why This Approach Deserves Serious Attention
The day before WAIC opened, Dongfang Suanxin (Oriental Compute) launched the world's first software-defined near-memory compute 3D AI chip, the DF1000, in Pudong. The booth proclaimed: "14nm ≈ 4nm."
This doesn't mean 14nm process achieved 4nm transistor performance. Rather, it achieves an equivalent experience at the system level through two technical approaches. Before understanding these approaches, we need to understand the two core bottlenecks facing domestic chips:
Bottleneck 1: Advanced process nodes are blocked. U.S. export controls restrict China's access to manufacturing capability below 7nm. China's most advanced mass-production process remains at 14nm. Under process restrictions, the path of shrinking transistor dimensions to improve performance is closed.
Bottleneck 2: HBM supply chain is constrained. High Bandwidth Memory (HBM) is a critical AI chip component, determining how fast a chip can read data from memory. HBM manufacturing is highly concentrated among Samsung, SK Hynix, and Micron, and subject to export controls. Without HBM, domestic chips face a hard bandwidth ceiling.
DF1000's two technical approaches precisely bypass these two bottlenecks.
Approach 1: Software-Defined Chip
Traditional chip design is "hardware-fixed function"—once a chip is taped out, the compute units' functions are locked. To change functionality, you must redesign and re-tape-out.
A software-defined chip is fundamentally different: the chip hardware itself has no fixed functions—it is dynamically configured by software. The core principle is "spatial parallelism + time-division multiplexing"—the same piece of silicon can be reconfigured at different moments as a matrix multiply unit, a vector processing unit, or a communication controller.
What does this mean?
Model algorithms iterate significantly roughly every three months. Traditional chip design-to-tape-out takes 12–18 months—by the time the chip is manufactured, the algorithm has gone through three generations. The GPU solution is a general-purpose processor (SIMT architecture) that can do everything but at an efficiency discount. The software-defined chip approach is more radical: let the hardware follow the software, reconfiguring into optimal form at every runtime.
The benefits are obvious: extremely friendly to model architecture iteration—no re-tape-out needed. The costs are equally obvious: the "flexibility tax" of reconfigurable architecture—a lower proportion of transistors on the same die can be used for pure computation.
Why? Because reconfigurable architecture requires extensive configuration memory (recording what the hardware should do at any moment), programmable interconnect networks (connecting different compute units), and configuration controllers. These are all "management overhead"—they occupy silicon area without directly producing compute. Using FPGA as a reference: in a typical FPGA, approximately 50–70% of the area is programmable interconnect and configuration memory, with only 30–50% being actual compute logic. This is why, at the same process node, FPGA compute density is only 1/5 to 1/10 that of ASIC.
A software-defined chip finds a balance between FPGA and ASIC. It's more efficient than FPGA (coarser configuration granularity, smaller interconnect overhead) and more flexible than ASIC (runtime reconfigurable). Wei Shaojun did not disclose the specific "management overhead" ratio at the launch event, but 20 years of academic research suggest this trade-off has been deeply optimized.
This means the "14nm ≈ 4nm" claim should be understood as:
Number 1: A 4nm ASIC's compute density is approximately 8–10× that of a 14nm ASIC. This estimate is based on TSMC's published transistor density data (N14 ≈ 30 MTr/mm², N4 ≈ 140–180 MTr/mm², a density ratio of roughly 5–6×), plus frequency improvement (~1.3–1.5×) and architectural improvements (~1.2–1.3×), totaling approximately 8–10×. This is the physical ceiling of the process gap.
Number 2: The management overhead of software-defined architecture. FPGA is the extreme reference (50–70% area for configuration and interconnect). Software-defined chips have coarser configuration granularity and smaller interconnect overhead. Wei Shaojun did not disclose the specific ratio at the launch, but 20 years of academic accumulation indicate this trade-off has been deeply optimized. A reasonable assumption is management overhead in the 30–50% range (i.e., compute logic occupies 50–70% of die area).
Number 3: The combined boost from near-memory compute + dynamic reconfiguration. Hybrid bonding pushes access bandwidth to 6.4 TB/s (exceeding HBM3e's 4.8 TB/s), reducing idle time when compute units wait for data. Dynamic reconfiguration keeps hardware resource utilization high under variable loads. The combined boost is roughly estimated at 3–5× effective compute improvement, but this depends on specific workload characteristics.
Three numbers stacked: 14nm software-defined chip effective compute density ≈ 14nm ASIC density × (1/0.5) × 3–5 ≈ 6–10× of 14nm ASIC, approaching the 8–10× of 4nm ASIC. This derivation shows that "14nm ≈ 4nm" isn't magic—it's the compound effect of two technical directions. But it also shows this equality has a wide error band: under ideal workloads it may hold; under unfavorable workloads it may only reach 60–70% of 4nm.
This technical approach originates from the Institute of Microelectronics at Tsinghua University, developed over 20 years since 2006. CEO Wei Shaojun is a professor at Tsinghua's Institute of Microelectronics and a leading academic authority in Chinese chip design. This isn't a startup starting from scratch—it's the industrialization of 20 years of academic accumulation.
Approach 2: 3D Stacked Near-Memory Compute
This is the truly intriguing part.
In traditional chip architecture, compute units and memory are separate—data must travel from memory through PCB traces to compute units, and back after processing. In this process, data movement consumes far more energy and time than computation itself. This is the "memory wall" problem.
How severe is it, specifically? A single 64-bit floating-point multiply consumes approximately 1 nanojoule. Reading a 64-bit data element from HBM to the compute unit consumes approximately 100–200 nanojoules—100–200× the computation itself. This means that in large-model inference, the vast majority of energy and time isn't spent on "computing" but on "moving data."
The industry's mainstream solution is HBM—stacking memory and compute chips together via TSV (Through-Silicon Via) and micro-bumps in a 3D configuration, shortening the physical distance. But the HBM supply chain is constrained.
DF1000 takes a more aggressive path: DRAM-Logic wafer-level Hybrid Bonding 3D vertical packaging.
Where's the difference? To understand it, we need to compare the physical parameters of both approaches:
Traditional HBM 3D stacking uses micro-bumps to connect DRAM layers and logic layers. Micro-bump pitch is typically 30–50 μm. At this pitch, the number of interconnect channels per unit area is limited—a typical HBM3 chip has approximately 5,000–10,000 TSV interconnect channels, providing approximately 3.35 TB/s of bandwidth.
Hybrid bonding doesn't use bumps. Two wafer layers are bonded directly at the copper-to-copper interface, with pitch at the sub-micron level (less than 1 μm; advanced processes achieve 0.4–0.9 μm). At this pitch, the number of interconnect channels per unit area is 100–1000× that of the micro-bump approach.
The increase in channel density directly translates to bandwidth improvement—this is why DF1000 uses conventional DRAM (not HBM) yet achieves 6.4 TB/s access bandwidth, surpassing HBM3 (3.35 TB/s) and HBM3e (4.8 TB/s).
But there's no free lunch in physics. Hybrid bonding has a hard constraint: thermal dissipation. After the DRAM layer and logic layer are bonded together, heat generated by the logic layer must pass through the DRAM layer to dissipate. DRAM is temperature-sensitive (operating temperature typically required to be < 95°C); under high load, logic-layer heat may push DRAM into unsafe temperatures, triggering thermal throttling that reduces bandwidth and frequency.
DF1000's thermal solution wasn't disclosed in detail. Possible approaches include: using thinner DRAM layers (reducing thermal resistance), adding thermal interface materials between logic and DRAM, or adopting liquid-cooled packaging. How well this problem is solved directly determines how much of the 6.4 TB/s can be sustained under continuous high load.
Roadmap: DF2000 by end of 2026, DF3000 in 2027, targeting to surpass Nvidia H200 and B300 respectively.
Questions That Need Verification
DF1000's technical approach is imaginative, but several key questions require real deployment data to answer:
1. What is the effective compute (MFU)?
520 TFLOPS is peak. Effective compute depends on the software-defined architecture's reconfiguration overhead—how many clock cycles does each function switch cost? In the alternating All-to-All communication and expert computation pattern of MoE models, will frequent function switching consume too much time? Wei Shaojun himself said "what matters more isn't the lab peak number"—this is correct, but the real test is MFU data from user deployments.
Reasonable benchmark: GPU MFU in large-model training is approximately 45–55%. If the DF1000's software-defined architecture can maintain 40%+ MFU, it's approaching the practical threshold. Below 30% means the "flexibility tax" is too heavy.
2. Compute per dollar and compute per watt
14nm wafer cost is low—but the software-defined architecture requires more configuration memory and interconnect networks, potentially resulting in a larger die (large dies at 14nm face yield challenges). Furthermore, hybrid bonding 3D packaging cost isn't trivial—wafer-to-wafer bonding requires both wafer layers to have near-100% yield (otherwise one bad chip scraps the entire wafer). Whether the final compute-per-dollar ($/TFLOPS) is genuinely competitive can only be judged after mass-production pricing.
3. The software ecosystem valley of death
The company claims compatibility with mainstream deep learning frameworks and provides a full-stack CAAP software toolkit. But there's a large gap between "compatible" and "efficiently optimized." Huawei's CANN ecosystem took years to reach its current maturity. Dongfang Suanxin, founded in 2024, has software ecosystem maturation speed as its biggest unknown.
Specifically: deep learning frameworks (PyTorch/TensorFlow) backends need to adapt operator implementations for each chip architecture. GPUs have CUDA providing a unified abstraction layer, so frameworks only need to target CUDA. Domestic chips must either build their own CUDA-equivalent abstraction layer (Huawei's CANN, Moore Threads' MUSA) or go through intermediate representations like OpenAI Triton or LLVM. Which path Dongfang Suanxin's CAAP takes, how many operators it covers, and what performance level it's tuned to—these directly determine the distance between "usable" and "good."
4. From 128 cards to large-scale clusters
Currently demonstrated with stable operation of a 128-card cluster. Scaling from 128 to 512 to 1,024 cards, engineering problems in interconnect topology, routing strategy, fault isolation, and memory consistency grow nonlinearly. Supernode players have much deeper accumulation in this dimension.
Assessment
DF1000's significance isn't whether it can immediately beat Nvidia. It's that it proves the feasibility of a technical approach: since advanced process nodes are blocked, make up the difference through architecture innovation and advanced packaging.
Huawei uses the Lingqu interconnect to compensate for single-chip process disadvantages—a system-level approach. Moore Threads uses engineering capability to prove domestic chip training feasibility—an ecosystem adaptation approach. Dongfang Suanxin uses software-defined compute + 3D near-memory compute to bypass process and HBM bottlenecks—a fundamental architecture innovation approach. Three different directions, identical strategic logic: under the constraint of restricted process technology, rebuild performance competitiveness through architecture and system innovation.
This isn't a passive response—it's an active choice of a different efficiency curve.
Observation 4: Embodied Intelligence's "8-Hour Standard"—The Gap from Demo to Productivity
Why the Evaluation Standard Matters
Embodied intelligence was one of WAIC 2026's twin cores, with 200+ companies exhibiting. But more important than the number is the shift in the industry's acceptance standard.
The "8-hour standard" isn't a technical metric proposed by any single company—it was a tacit consensus across the entire exhibition floor. From Keenon to AgiBot, from Ant Lingbo to Elite Robotics, every booth's narrative shifted from "look, my robot can do this" to "look, my robot does this every day in a real scenario, for 30 days straight."
This shift signals the industry is crossing a critical engineering chasm: from "demonstrating feasibility" to "proving reliability."
Completing a task loop in a lab requires solving the perception → planning → execution chain. Running continuously for 8 hours on a real production line requires solving an entirely different set of problems. Why is 8-hour continuous operation so much harder than a single demo?
Because real-world disturbances follow a long-tail distribution. In a single demo, objects are in fixed positions, lighting is constant, nobody suddenly walks into the workspace. But during 8 hours on a real production line, a robot encounters: lighting changing from morning daylight to afternoon western exposure, dimensional variation between workpiece batches, conveyor belt micro-vibrations causing visual blur, the operator from the adjacent station occasionally entering the work area, sensors drifting after 4 hours of continuous operation.
Each of these disturbances is non-fatal in isolation, but their combinatorial space is exponential. A system that succeeds 100% of the time across 100 demos may fail in 8-hour continuous operation upon encountering an unforeseen disturbance combination. This is why there's a 1–2 order-of-magnitude engineering gap between "99% lab success rate" and "8-hour uninterrupted production-line operation."
What Changed Technically
VLA (Vision-Language-Action) models have become the mainstream architecture. Traditional robotics pipelines are modular: first object detection (perception), then path planning (cognition), finally joint angle generation (execution)—three modules using different models, connected by hand-crafted interfaces. VLA unifies visual understanding, language reasoning, and action execution into a single end-to-end neural network. Input is camera imagery and language commands (e.g., "put the red cup on the left"); output is angle and force commands for each joint. Training data comes from teleoperation demonstrations: humans control robots to complete tasks via VR controllers or motion-capture gloves, and the system records "what it saw → what it did" paired data. After training, the model can generalize to objects and scenes unseen during training. Keenon demonstrated a VLA architecture integrated with a world model. Ant Lingbo's LingBot-VLA is a cross-embodiment foundation model—enabling robots of different morphologies (articulated arms, wheeled, humanoid) to share the same operational capabilities.
Why does cross-embodiment learning matter? Because the biggest bottleneck in embodied intelligence isn't algorithms—it's data.
A human infant learns basic manipulation through approximately 1,000 hours of free exploration. How much data does a robot need to reach equivalent operational capability? Current estimates are approximately 1,000–10,000 demonstrations per task—and that doesn't account for generalization across environmental variations. If every robot must learn from scratch, data collection costs are unsustainable.
The logic of cross-embodiment learning: let robots of different configurations share the same "brain." The underlying representation of a "grasp cylinder" skill learned by a humanoid robot in a factory can be transferred to a wheeled articulated arm. This way, data from 100 differently-configured robots feeds the same foundation model, rather than each robot training independently.
Data collection costs are thereby drastically amortized. This is also why Ant Lingbo can achieve 3 robots of different configurations working collaboratively in the pharmacy scenario—they share the cross-embodiment capability of LingBot-VLA.
Long-sequence task loops are maturing. Fourier GR-3 completes "grab apple → find plushie" long-sequence tasks in home scenarios—meaning the system can not only execute individual actions but also maintain goal tracking and state management across multi-step tasks.
The technical difficulty of long-sequence tasks lies in error accumulation. Each step has a certain failure probability. If each step succeeds at 95%, a 10-step chained task has only 60% composite success rate. To achieve 95% composite success on a 10-step task, each step must achieve 99.5% success. This means long-sequence tasks impose far higher single-step reliability requirements than demo-level performance.
Ant Lingbo's pharmacy scenario goes further—3 heterogeneous robots collaboratively complete a multi-step workflow within 90 seconds. Multi-robot coordination introduces additional communication and synchronization overhead, but also provides fault-tolerance opportunities: if one robot fails, another can take over.
Industrial-grade precision is reaching the threshold. Elite Robotics Centaur-G1's ±0.1 mm repeat positioning accuracy meets the requirements of precision optical communications manufacturing. Going from "can grab things" to "can do precision assembly" is a qualitative leap—the latter typically requires tolerances of 0.05–0.5 mm, while the former only needs to be within 1–5 cm to count as success.
The Basis for the "12–24 Month" Estimate
"From proposing the 8-hour standard to achieving it at scale requires 12–24 months"—this time estimate isn't a shot in the dark. It can be derived from several observable variables:
Variable 1: VLA model data accumulation speed. Current VLA foundation model training data comes primarily from teleoperation demonstrations and simulation environments. Teleoperation collection speed is approximately 100–500 episodes/person/day (depending on task complexity). Assuming a 50-person data collection team, daily output is approximately 10,000 episodes. Over a year, that's approximately 3 million episodes—sufficient for basic manipulation skill generalization, but still inadequate for long-tail scenario coverage. At this rate, reaching "industrial-grade 95% success rate" requires approximately 2–3 rounds of data iteration (6–8 months each).
Variable 2: Deployment feedback iteration cycle. After each batch of robots is deployed to real scenarios, failure cases must be collected, root causes analyzed, models updated, and redeployed. A complete iteration cycle takes approximately 2–3 months (including data collection + model retraining + regression testing + on-site updates). To iterate from an initial success rate in a new scenario (typically 60–70%) to 95%+ production grade requires 4–6 iterations = 8–18 months.
Variable 3: Hardware reliability verification. Continuous 8-hour operation is also a test for the hardware itself—reducer wear, motor temperature rise, cable fatigue. Humanoid robot MTBF (Mean Time Between Failures) currently sits mostly in the 200–500 hour range. To meet the standard of 8 hours of daily continuous operation with monthly maintenance, MTBF needs to be at least 240 hours—just at the lower bound of current levels. Reaching 500+ hours requires approximately 12 months of hardware iteration.
Taking the longest path across all three variables, the time window for "achieving the 8-hour standard at scale" is 12–24 months. In an optimistic scenario (fast data accumulation + good hardware reliability), it could be 12–15 months; in a conservative scenario (slow long-tail coverage + hardware issues), it could require 20–24 months.
Anchoring the Policy Targets
Shanghai's announced target: deploy 100,000 humanoid robots into factories by the end of the 15th Five-Year Plan. In 2026, China's humanoid robot annual production is expected to exceed 100,000 units.
But from production volume to deployment to effective operation, there is an enormous gap. The 100,000-unit production figure is a supply-side number. What truly matters is: how many robots are operating in real scenarios for over 30 consecutive days, for more than 4 hours per day, with task completion success rates above 95%?
Nobody has published this data yet. A reasonable inference: the number of robotic deployments that can achieve 30 consecutive days of stable operation is currently orders of magnitude smaller than the production volume. Most robots are still in the "deploy → debug → redeploy" cycle.
The very proposal of the "8-hour standard" signals that the industry has recognized this gap. But between proposing a standard and meeting it, time is still needed.
IV. Inflection Signal for Token Economics
Bringing all four threads together, one convergent signal deserves to be called out: the business model for Token pricing is undergoing a qualitative shift.
Alibaba Qwen launched "peak/off-peak Token" pricing—users get up to 80% off between 10 PM and 8 AM. This pricing model is borrowed from peak/off-peak pricing in electricity markets.
Why do electricity markets have peak/off-peak pricing? Because the marginal cost of power generation differs enormously between peak and off-peak periods—at peak, expensive peaker plants must be started; at off-peak, baseload plant capacity is surplus. Peak/off-peak pricing shifts demand toward off-peak periods, improving overall utilization.
What does peak/off-peak Token pricing signal?
To understand this signal, we first need to think through: why does AI inference cluster utilization fluctuate day and night?
Based on industry experience estimates, large API providers' inference clusters have average daily utilization of approximately 40–60%. During daytime peak (8–10 working hours), utilization can reach 80–95%; during nighttime off-peak (approximately 14–16 hours), utilization may drop to 20–30%. This means that for 30–40% of each day, the majority of cluster compute is idle.
Inference cluster capacity is provisioned for peak demand. Daytime is when enterprise users hit APIs hardest—Agent tasks, data analysis, customer service conversations, and content generation all concentrate during working hours. At night, enterprise calls drop, but cluster compute doesn't automatically shut down (GPU/NPU shutdown and restart requires loading model weights, taking minutes to over ten minutes—it's better to keep them idle and on standby).
This means that at night, large amounts of compute are "spinning"—depreciation continues, electricity costs continue, but no tokens are produced. If this idle nighttime compute could be sold at 80% off to latency-insensitive batch tasks (log analysis, offline translation, data cleaning), the "idle cost" transforms into "marginal revenue."
Alibaba's introduction of this pricing signals that utilization fluctuation on the inference supply side has become a management problem worth optimizing. If inference cluster scale were still small and running at full capacity day and night, there would be no incentive for peak/off-peak pricing. Its emergence indicates that inference capacity has reached a scale where the question has shifted from "how to expand capacity" (a construction problem) to "how to improve utilization" (an operational efficiency problem).
Combined with the supernode-driven 40–60% compression in inference cost analyzed earlier—inference capacity expansion will accelerate (unit cost decline → more deployment), but utilization management pressure will also intensify (capacity growth may outpace demand growth). This mirrors the cycle the photovoltaic industry experienced: rapid capacity expansion → price wars → leading companies survive through economies of scale and cost advantages → tail companies exit.
The trajectory of Token prices is therefore not a monotonic decline, but a step-wise decline accompanied by periodic price wars. Each new generation of compute infrastructure (supernodes, new-architecture chips) triggers a round of price warfare, pushing Token prices down a step. Then demand catches up to supply, and prices briefly stabilize. Then the next round begins.
Alibaba's peak/off-peak Token pricing at 80% off is the early signal of the first price war.
V. Assessment
WAIC 2026 refracts the following trends in China's AI industry:
First, the logic of competition has shifted from "chasing process nodes" to "architecture innovation + system efficiency." Huawei uses the Lingqu interconnect to compensate for single-chip process disadvantages—a single Ascend 910C's FP16 compute is approximately 1/3 of Nvidia's B200 (based on public spec comparison), but at the system level, effective compute share is pushed from 30–45% to 70–85%. Moore Threads uses engineering capability to prove domestic chip training of trillion-parameter models is feasible—Meituan used 2023 vintage chips to train LongCat-2.0; the bottleneck was never just hardware. Dongfang Suanxin uses software-defined compute + 3D near-memory compute to bypass process and HBM bottlenecks—hybrid bonding's channel density is 100–1000× that of traditional micro-bumps, achieving bandwidth exceeding HBM3e with conventional DRAM. Three routes, identical strategic logic: under the constraint of restricted process technology, rebuild performance competitiveness through architecture and system innovation.
Second, the industry has switched from "can it be done?" to "does it make money?" Foundation models no longer compete on parameters—they compete on Token pricing models. Robots no longer compete on backflips—they compete on production-line shift hours. Agents no longer compete on demo polish—they compete on end-to-end task completion rates. AI4Science no longer competes on papers—it competes on how much R&D cycle time was compressed.
Third, inference costs have substantial room for decline. Supernodes' 3× single-card inference efficiency improvement directly compresses compute depreciation (the largest single component of Token marginal cost), compounded by inference frameworks' independent 20–30% annual improvement. But operations, data, and bandwidth are unaffected. Overall, Token prices will decline 50–70% over 18–24 months—not to "cabbage levels," but in a step-wise pattern accompanied by periodic price wars.
Fourth, the domestic chip training-side "0 to 1" is complete. Meituan LongCat-2.0 is the hardest evidence. The breakthrough happened now rather than earlier because MoE architecture changed communication patterns (from AllReduce to All-to-All, circumventing domestic chips' bandwidth weakness), inference-side engineering accumulation fed back into training, the software stack crossed its payoff tipping point, and sanctions forced ecosystem closure. "1 to 10"—training costs genuinely reaching GPU parity—depends on MFU improvement speed, estimated at 12–18 months.
Fifth, the "8-hour standard" in embodied intelligence is the most memorable industry consensus to emerge. The pivot from "demonstrating feasibility" to "proving reliability" has begun. Based on VLA data accumulation speed (6–8 months per round), deployment feedback iteration cycles (2–3 months per round, 4–6 rounds needed), and hardware reliability verification (MTBF from 200–500 hours to 500+ hours, approximately 12 months), the time window for achieving the 8-hour standard at scale is 12–24 months.
WAIC 2026 was not a "flex your muscles" carnival. The exam has only just begun.
Sources: WAIC 2026 official press conference and exhibition floor coverage (China Industry & IT News, The Paper, Yicai, Southern Metropolis Daily, Xinmin Evening News, Eastday, TMTPost, China Times, China Business Journal, IT Times, Science and Technology Innovation Board Daily, Red Star Capital Bureau, Blue Whale News, et al.), official releases and technical materials from Huawei/Sugon/ZTE/Dongfang Suanxin/Meituan/Moore Threads, CAICT Supernode Development Report, CITIC Securities WAIC 2026 preview research report, and Omdia analyst commentary. BOM cost breakdown is an estimate based on publicly available information and does not represent precise figures. Data as of July 18, 2026.
This article does not constitute investment advice.