At the AI Infra Summit, which opens in Santa Clara on September 15, Marvell's keynote speaker is one Dave Lazovsky. The name deserves half a second's pause: he is the founder and CEO of Celestial AI, the optical interconnect startup Marvell agreed to acquire last December and closed this February, and he now runs Marvell's entire data networking business unit, taking the stage as executive vice president to present "AI Inference at Scale." When an established chip company lifts an acquired founder onto its keynote stage, it usually says exactly one thing: the acquisition is the company's strategy itself.
That is the board this article takes apart. Marvell is trying to turn "everything between the XPUs" (every movement of data from compute unit to compute unit, from memory to compute, from rack to rack) into revenue on its own income statement. On the board sit three product lines, a $3.25 billion acquisition, and a warrant worth up to $12.2 billion, while the industry-wide migration of the bottleneck has set the direction for every move played.
1. Three Migrations of the Bottleneck: From Buying Compute to Buying Movement
Over the past three years, the center of gravity in the AI infrastructure story has moved three times.
2023 was the compute arms race. Every link in the supply chain priced compute density per unit of space; getting the cards meant getting everything, and networking and memory still counted as facilities. 2024 belonged to networking. A single rack could no longer hold the model, and the scale-up / scale-out layering became the datacenter's new grammar: inside the rack, a high-speed domain carries the accelerators; between racks, Ethernet weaves the cluster together; and the network was promoted from facilities to a primary architectural variable. In 2025 the memory wall became consensus, and the capacity gap between KV cache and HBM pushed "cost per bit" onto the agenda. By 2026 the three curves have compounded into a fourth bottleneck: the movement of data among compute, memory, and storage itself.
The mechanism by which movement becomes the bottleneck is not abstract. The more accelerators get stacked, the more per-card utilization depends on the speed at which data is fed in: weight synchronization, gradient aggregation, cross-card communication, memory paging, each of them manufacturing idle cycles of "compute waiting for data." Meta's largest single F16 fabric cluster takes 5,664 switches; a 100K-card-class cluster counts its optical links by the hundred thousand; and Colossus 2, on Musk's own stated scale, targets the million-card class. Once the base is that large, the absolute cost of idle spinning becomes a financial-report problem: FLOPs bought and left waiting on the network deliver negative return on investment.
Inference runs this account at finer resolution. Training's communication patterns are relatively regular, with gradient synchronization concentrated at step boundaries; inference traffic is fragmented: prefill and decode differ in latency sensitivity, KV caches migrate, get reused, and get evicted across instances, and batch carpools are dissolved and re-formed at any moment. The same card might tolerate ninety percent utilization in a training cluster; in an inference cluster, the utilization ceiling is set directly by the tail latency of data movement. Optical modules' share of cluster cost has climbed into double digits (industry estimates), a share that previously sat under facilities overhead. Interconnect vendors' messaging has therefore converged on three commercial words: utilization, token efficiency, return on investment. All three say the same thing: the marginal return on compute spending is now decided by the capacity to move data.
Marvell's press release on the eve of the Summit states this migration in plain terms: the ability to move data efficiently between compute, memory, and storage has become as important as compute itself; the interconnect now sits at the center of AI infrastructure performance, shaping bandwidth, latency, and power, and ultimately determining the economics of deploying AI at scale. From a startup, that sentence could pass as narrative; from a company holding incumbent share in optical DSPs and Ethernet switching, it is a battle cry.
A side proof comes from the exhibitor list. On this Summit's floor plan, beyond NVIDIA, Broadcom, and Marvell stand Lightmatter, Ayar Labs, Ciena, Credo, Micron, and d-Matrix; optical interconnect and memory-movement companies have all but booked out the hall. When interconnect vendors take up most of the headliner list at an "AI infrastructure summit," "movement is the next battlefield" has already moved from analyst judgment to exhibitor budget.
2. Three Product Lines and One Acquisition: Turning Every Meter of Movement into a Catalog
The six demos in Marvell's announced Summit lineup sort neatly into three lines, each mapping to one segment of data movement.
The first line handles movement, covering every meter that data travels. Inside the rack: a 256-lane PCIe 6.0 switch, pulling more accelerators and devices into the same scale-up system. The niche of PCIe switching and retimers has long been divided three ways among Marvell, Astera Labs, and Broadcom; AI racks have turned it from a server accessory into a main battlefield. Inside the cluster: Teralynx T100, a 102 Tbps Ethernet switch chip; this generation doubles the bandwidth straight into the hundred-terabit class, aligning with the top tier of Broadcom's Tomahawk 6 and aiming at the bandwidth and efficiency of large-scale AI networks. Over longer distances: Marvell's optical module DSP family and electrical repeaters. The PAM4 DSP market has long been split between Marvell and Broadcom, with the coherent and coherent-lite variants covering inter-campus and cross-metro links; storage access joins the same line, with DPUs and Ethernet switching providing network-wide NVMe access and a PCIe 6.0 NVMe SSD controller aimed at next-generation enterprise and AI storage. The lineup makes the three combat distances explicit (scale-up, scale-out, scale-across: in the rack, in the cluster, between campuses); not one meter is left out.
One detail is worth recording: Marvell's December acquisition press release also names UALink: its body states that these multi-rack fabrics demand purpose-built switches and protocols such as UALink, and the Data Center Group president's quote speaks of "our UALink scale-up switch roadmap." In the split where NVIDIA builds its wall with NVLink and AMD leads the industry's breakaway UALink standard, Marvell is betting on both sides. That is no surprise: it sells movement itself and takes no side in the protocol war; whichever standard wins, the physical-layer and switch-layer business lands with it. It also pays to see who stands at the other end of the table: nearly every one of the three lines faces the same rival, Broadcom, with Tomahawk 6 against Teralynx, the PAM4 DSP duopoly split two ways, and the seat of Google's lead TPU design partner still firmly in Broadcom's hands.
The second line handles the memory fabric, and its most important piece was bought. Photonic Fabric uses optical interconnect for cross-rack memory sharing, pushing the distance constraint on memory pools outward; the CXL family covers memory expansion, compression, pooling, and near-memory acceleration, with the official positioning landing on reducing the movement of AI datasets between XPUs and accelerating large-scale vector databases. Note the wording: the selling point of the memory products also lands on "movement." What can't be moved is cost; what can be moved is memory.
The third line handles observability. The RELIANT interconnect telemetry platform provides real-time visibility into the health of optical and electrical links, watching physical-layer health metrics, with the goal of shortening deployment time and post-failure mean time to repair. This line draws the least attention, and it is the most honest: when links are counted by the hundred thousand, interconnect failures and degradation happen daily, and being able to see the link is the precondition for operating one. Meta fills kernel blind spots with a dozen-plus eBPF probes in RDMATracer, doing the same job: the observability front line is advancing from the host into the link, and whoever builds the interconnect layer's stethoscope first adds one more strand of product stickiness.
The origin of the memory-fabric line deserves its own telling, because it is the most expensive move on the whole board. On December 2, 2025, Marvell announced the acquisition of Celestial AI: cash plus stock, transaction value $3.25 billion, with foreign media counting up to $5.5 billion including performance terms; the deal closed in February 2026. The company was founded in 2020 by two industry veterans: Lazovsky ran a billion-dollar-scale equipment business at Applied Materials, and his earlier startup Intermolecular made it to an IPO; co-founder Preet Virk came up through the front lines of communications silicon at Mindspeed and Macom. Originally named Inorganic Intelligence, the company raised more than $500 million over five years ($56 million in February 2022, $100 million in July 2023, $175 million in March 2024, $250 million in March 2025, with BlackRock joining the final round). Its core asset is Photonic Fabric: a multi-chip interconnect architecture with light as the medium. Its basic building block is the OMIB, the optical multi-chip interconnect bridge, claimed to deliver direct optical connection from any point on any die to any point on another die; above it, PFLink and CXL decouple memory out of the host boundary. Marvell's financial guidance is restrained: a $500 million annualized revenue run rate in Q4 fiscal 2028, with non-GAAP accretion landing in the second half of fiscal 2028. CEO Matt Murphy's line: scale-up is becoming the next frontier of AI infrastructure, the acquisition expands Marvell's addressable market in scale-up interconnect, and it accelerates delivery of the industry's most complete connectivity platform.
Put the acquisition next to the booth exhibits and the structure comes into focus. Marvell's incumbent strengths sit in scale-out (Ethernet switching, optical DSPs) and custom ASICs; scale-up and the memory fabric were the gaps. Celestial AI fills exactly those gaps, and it brought more than patents and products: the founding team came along. Lazovsky now heads the data networking business unit, Virk is SVP of the optical fabric business unit, and CTO Philip Winterbottom joined alongside. The "cross-rack memory sharing" demo in the announced lineup is, in essence, the acquired assets' first public appearance as an integrated whole. The founder of the acquired company is the one about to take the keynote stage, which says exactly that.
3. CXL Revives by Way of Vera: The Memory War Moves Between Racks
Of the three lines, the memory fabric most deserves its own section, because a key fact landed on September 9.
On September 9, Marvell announced that Structera X, its CXL memory expansion controller, has completed interoperability with the NVIDIA Vera CPU platform. The blog's own words deserve quotation: memory has become the defining constraint of modern AI infrastructure, "there is never enough DRAM"; and the value of a CXL memory expander depends on how wide a spectrum of platforms it can run on.
CXL's situation over the past two years has been the industry's standard case of "right, but early." Around 2021 it was expected to be the general answer to server memory disaggregation; it then lived through slow CPU-side support, a fragmented ecosystem, and the latency-tax controversy, and the doomsayers for a time held the mainstream. The protocol's own roadmap kept moving the whole time: the 1.1 era did device attachment, 2.0 brought switching, 3.0 completed pooling and memory semantics; the on-paper capability set has been ready for a long while. What kept stalling was platforms and software. The arithmetic of disaggregation was never hard: expanded DRAM costs several times less per GB than HBM. The hard part was that without official support from a mainstream CPU platform, even the best expansion controller could only circle inside niche systems. The validation matrix Marvell has now put on the table is its answer to that history: on the CPU side, Intel Xeon and AMD EPYC, now with NVIDIA Vera added; on the memory side, the big three of Micron, Samsung, and SK hynix. The product family stands complete in three tiers: Structera X runs expansion, Structera A runs near-memory acceleration, Structera S runs rack-scale pooling over CXL switching. The specifications are published: Structera S 30260 offers 260 lanes of PCIe 6.0/CXL 3.x, 16 to 32 hosts, a 48TB shared pool, 4TB/s of bandwidth, and round-trip latency under 460 nanoseconds, sampling this quarter; Photonic Fabric's official numbers are 50 meters of reach, 32TB of warm KV cache, and 2 to 3 times token throughput.
The Vera square matters most. It is the Arm CPU NVIDIA paired with the Rubin generation, and the Vera Rubin platform carries the mainline inference workloads beyond the NVLink domain. NVIDIA letting a third-party CXL controller attach to its own CPU amounts to granting memory disaggregation a formal residence permit inside its own ecosystem. The judgment here: CXL's value has always depended less on protocol efficiency than on whose platform it runs on. Once an ecosystem wall has opened a door in its own interest, it very rarely closes again for others; and the interop square Marvell announced is an established entry point into the NVIDIA ecosystem.
NVIDIA's motive is not hard to read either. The marginal cost of the per-rack HBM pool keeps rising, and given that NVIDIA does not make DRAM, steering memory disaggregation into CPU-side coordination is its most economical capacity-expansion path: the KV caches and vector indexes of inference workloads are natural fits for tiered placement, hot data staying in HBM, warm data stepping down into the CXL pool, cold data settling onto NVMe. For Marvell, the value of this square is that it activates assets on both flanks at once: the CXL controllers gain the largest platform endorsement there is, and Photonic Fabric gains the interface narrative for entering NVIDIA racks.
The assault on the memory wall had so far concentrated inside the chip, along four routes: HBM for capacity, 3D stacking for density, tiered memory for bandwidth, compression for utilization. Structera and Photonic Fabric open a fifth: trade disaggregation for capacity, trade optics for distance, and turn the memory pool from an asset private to one server into a resource shared across a rack group. The war inside the chip is decided by the three memory makers and packaging process technology, and that landscape is settled; the war between racks has just opened. The other side of the coin also needs stating: pooled memory widens the failure domain from a single machine to a rack group, and one failed CXL switch can freeze warm-data access for a whole row of servers; until the operations model and software stack mature, hyperscalers will not casually stake core workloads on it. With the acquisition, Marvell holds the first-mover's ticket into the game, but between the entry ticket and the won game stands ecosystem execution, and that is not something an acquisition can buy.
4. Google's Wager Structure: 240 Vesting Tranches at $500 Million Each
Beyond the product catalog, this ledger has a financial side. The 8-K Marvell filed with the SEC on August 19 turned an agreement signed in late July into public information, and its structure deserves a clause-by-clause reading.
On July 29, Marvell and Google signed a commercial agreement covering a set of custom silicon projects around Google's TPU ecosystem: AI inference accelerators, storage controllers, network interface controllers, memory interface controllers, and near-memory compute. On August 18, Marvell issued Google a warrant: up to 58,970,907 shares, exercise price $206.58, roughly $12.2 billion if fully exercised, term of seven years, running to August 2033.
The crux is the vesting structure. Of the total warrant shares, only about 2.3% (1.36 million shares) vest on a time schedule, spread across four quarters; the remaining 97.7% is pegged to purchase performance. From the third quarter of fiscal 2027 through the end of fiscal 2033, each $500 million of purchases by Google unlocks one tranche, 240 tranches in all. Do the division: 240 tranches times $500 million means full vesting takes $120 billion in cumulative custom silicon purchases, about $19 billion a year. For reference, Marvell's total revenue in its past full fiscal year was about $8.2 billion, and its custom silicon revenue last year was about $1.5 billion: a full-vesting pace of roughly $19 billion a year is about twelve times that line's entire revenue last year. The warrant demands that a single business line grow to more than twice today's entire company within the roughly six-year vesting window.
Play the three pacing scenarios forward and the asymmetry of the structure comes into focus. If Google purchases $10 billion a year, six-plus years accumulate roughly $65 billion, unlocking just over half the shares including the time-vested portion; full vesting requires hitting the roughly $19 billion annual pace every single year, no exceptions; and if purchases slow to $5 billion a year, most tranches lapse worthless at the 2033 expiry, leaving Marvell with pipeline and narrative while Google has paid not a penny. Of the three scenarios, two run against Marvell; only the full-tranche scenario cashes in everything the press release promised.
Google's side of the ledger is figured just as finely. Each unlocked tranche corresponds to about 240,000 shares; if Marvell's share price by then sits meaningfully above the exercise price, the exercise right on each tranche is a net gain. It amounts to fitting the act of purchasing with a self-reinforcing subsidy machine: the more Google buys, the stronger the revenue narrative, the stronger the share price, and the more the unlocked warrant is worth. Purchasing, equity, and ecosystem lock-in, three separate things, are twisted together by a single document.
So the nature of this document needs to be stated precisely: an order states minimum purchase volumes, and this document does not. The disclosed scope is the companion projects around the TPU ecosystem; Broadcom remains the lead design partner for the TPU itself, a collaboration base of more than a decade is not shaken by this document, and what is being pried at is incremental share. This is a two-sided wager: Google trades purchases for equity upside, and Marvell trades shareholder dilution for pipeline stickiness. The bears keep one finer account: under accounting standards, this type of warrant is treated as a deduction from the transaction price, so every Google purchase that trips a tranche has its revenue first shaved down by a slice of the warrant's fair value. The financial engineering bites back into part of the very revenue it is meant to amplify.
Pull the camera back one frame and the family gained a second specimen this week: Nvidia is in talks to enter Anthropic's IPO as an anchor investor, with Anthropic seeking a valuation of around $2 trillion. Two specimens is a thin sample, but the grammar is already clear: in both of these deals, no purchase commitment was written and no check was cut; what was issued were arrangements pegged to equity upside. The structures differ, the grammar is kin, and the default shape of newly signed partnerships is sliding from obligation toward wager. Vendor financing ran a full boom-and-bust cycle in the telecom equipment era; the difference this round is that the stake has changed from debt to equity upside.
The market priced the bull case first: on the day of the news, Marvell rose more than 14% intraday (closing up nearly 10%), Broadcom fell more than 5%, and JPMorgan set an overweight rating. The real verdict dates are already on the calendar: October 6, Investor Day, where the market's line of $18 billion of FY28 revenue run rate faces its path check; and the third quarter of fiscal 2027, when we learn whether the first performance tranche triggers.
5. Summary and Judgment
This article was written on the eve of the AI Infra Summit. What Marvell brings to Santa Clara is a product list covering the three lines of movement, memory, and observability; a CXL interoperability threaded through to NVIDIA Vera; an optical interconnect asset bought for $3.25 billion; and a warrant with 97.7% of its shares riding on performance. Three judgments:
First, interconnect has gone from accessory to catalog. When one company can line up movement across the full scale-up, scale-out, scale-across distance map, plus a memory fabric and link telemetry, as a single procurable list, bottleneck migration graduates from analyst narrative into purchase-order structure. The people buying compute have begun drawing up movement budgets as a separate line; this category's ceiling is set by cluster scale, and no end is currently in sight.
Second, CXL needed NVIDIA, and now it has one. The Vera interop turns memory disaggregation from a protocol that spent two years being written off into an established entry point into the NVIDIA ecosystem. The memory war's battlefield has extended from inside the chip to between racks, and the second front has no hegemon yet; Marvell's acquisition of Celestial AI bought the first-mover's ticket in, but between that ticket and a won game stand years of ecosystem execution, with the warrant's seven-year term as the longest calendar anchor. The sharpest counterexample is the hyperscaler that builds its own: Meta did the same thing with an ASIC of its own design. Marvell's bet is that most players will keep buying the catalog, and self-built fabric stays the province of a few.
Third, the wager is replacing the promise as the grammar of AI capital. Google's warrant hangs 97.7% of its shares on purchase performance, and Nvidia's anchor investment in Anthropic turns capital itself into an equity-linked stake. The two ends share one trait: certainty has exited the deal; what is sold is the upside alone. Structures of this kind amplify good news and silence bad news, and each vesting disclosure will be a hidden thread for tracking Google's custom silicon share across the coming fiscal years.
Five follow-ups to watch, all on the calendar: whether Lazovsky's "AI Inference at Scale" keynote, over the three days of the AI Infra Summit, offers a new interconnect line for inference clusters; the FY28 annualized-revenue-path breakdown at the October 6 Investor Day; whether the warrant's first vesting tranche triggers in the third quarter of fiscal 2027; whether Broadcom's share of Google's custom silicon account begins to loosen; and whether NVIDIA itself confirms the Vera interop in official terms. All five are verifiable; when the time comes, check them back against this article's three judgments.
Declaration: This article draws on Marvell's official press releases and blogs (the 2026-09-09 Summit portfolio and the Structera X–Vera interop; the 2025-12-02 Celestial AI acquisition announcement), the Google warrant 8-K (SEC accession 0001193125-26-356217, filed 2026-08-19), and public reporting by CNBC, Tom's Hardware, and Seeking Alpha, among others. It is not investment advice. Data as of September 12, 2026.