Using NVIDIA Kyber NVL144 as a Benchmark to Reevaluate Huawei, H3C, and Dawning's Scale-Up Roadmaps
Whether an enterprise should purchase a supernode does not depend on whether a vendor can pack 1,024 cards into one system. It depends on four things: whether your primary model is already limited by communication bottlenecks, whether your existing data center can support hundred-kilowatt racks, whether your software team can absorb a platform migration, and whether the system can maintain sufficiently high effective utilization over the next three years.
This article does not rank vendors by card count or peak FLOPS. Instead, it analyzes which system layers each vendor controls, where they have transferred engineering complexity, and whether those choices are likely to reduce the effective cost per token under real training and inference workloads.
Introduction: The Supernode Solves Not "Not Enough Cards" but Inefficient Coordination of Compute
The most noteworthy change at WAIC 2026 was not the number of new domestic AI chips, but the fact that almost every major compute vendor shifted their product demo focus from individual cards and servers to supernodes. Huawei publicly demonstrated its 1,024-card Atlas 950 SuperPoD for the first time; ZTE partnered with Biren, M-Cloud, Enflame, and others to launch the OEX supernode; Biren showed a 1,024-card NPO optical interconnect solution; and Baidu, Alibaba Cloud, and others presented 64, 128, 256, and even thousand-card-class systems.
This shift is driven by the fact that large-model workloads have changed the boundaries of the computer itself. Traditional 8-GPU servers are organized around the CPU and PCIe. But in scenarios involving tensor parallelism, large-scale MoE, long-context inference, and Prefill/Decode disaggregation, GPUs or NPUs need to frequently exchange activations, gradients, token routing results, and KV Caches within very short time windows. At this point, the network is no longer an external facility connecting computers — it becomes part of the computer's internal structure.
The purpose of a supernode is to place more accelerators into a single Scale-Up (纵向扩展) domain with low latency, high bandwidth, and direct memory access between peers. The key question is not "how many cards are connected" but how many endpoints truly share a single low-latency communication domain; whether endpoints can use Load/Store, atomic operations, and a unified address space; and what happens when a single card, switch board, or optical link fails.
This article analyzes five technical dimensions, applies an L1-L4 maturity framework, provides enterprise decision guidance, and includes a concrete POC checklist. Complete Chinese version available at locsic.com.
I. Route Survey: Three Supernode Approaches
Three distinct routes can be observed: full-stack synergy (NVIDIA, Huawei), open Fabric & systems engineering (H3C, Dawning, ZTE OEX), and chip vendor upstream move (Biren, M-Cloud, Enflame, Moore Threads). Each makes different assumptions about industry division of labor and places complexity in different locations. The full analysis of each route is covered in the Chinese version.
II. Five Technical Dimensions
1. Scale-Up Interconnect
Under MoE workloads, every token may be dynamically routed to different experts, presenting the network with bursty, skewed, unpredictable All-to-All traffic. Traditional per-flow hash-based ECMP struggles with such micro-bursts, so cell-level spray (信元级喷洒), multi-path flow control, in-network computing, and topology-aware scheduling are entering the Scale-Up switching layer.
NVIDIA: Vera Rubin NVL72 is the realistic baseline — 72 Rubin GPUs, 36 Vera CPUs, 3.6TB/s NVLink per GPU, 260TB/s NVLink 6 switching, 20.7TB HBM4. NVIDIA's deepest moat is not these numbers but the fact that GPU ports, NVSwitch, topology, NCCL, runtime, and model frameworks are co-designed.
Huawei: CloudMatrix 384 (384 NPU + 192 CPU, UnifiedBus) is the starting point. Atlas 950 SuperPoD demonstrated 1,024 cards with 1 EFLOPS FP8, 256TB unified memory, 3μs RTT. 750+ CloudMatrix 384 units deployed. Full 8,192-card configuration planned for Q4 2026.
H3C: G-Link has evolved from protocol to chip and Fabric architecture across five layers: S80000 product, SUE protocol, GLink for 1,024-card, GT-Link endpoint chips, and GT-Fabric Scale-Up switching (144×112G lanes, ~300ns latency, supporting 8-8,192 card topologies).
Dawning: scaleX640 (640 cards, immersion cooling, 30-day stability test) demonstrates high-density systems engineering. scaleX40 (40 cards, 16U, 19-inch) addresses existing data centers.
2. Electrical and Mechanical Engineering
NVIDIA encapsulates complexity in the factory, leaving tray-level interfaces for the field. Huawei uses orthogonal electrical connection for short distances and inter-cabinet optical for longer ones. H3C emphasizes standard modules, blind-mate, factory pre-integration, and 800V HVDC. Dawning offers both extreme density (scaleX640) and standard box form (scaleX40).
3. Thermal Engineering
Thermal evaluation cannot stop at PUE. A system with PUE 1.05 but 50% GPU utilization may have higher per-token energy cost than one with PUE 1.15 and 80% utilization. Enterprises should test kWh per effective token, not just PUE.
4. System Architecture
Huawei's 950PR (128GB, 1.6TB/s, Prefill-optimized) and 950DT (144GB, 4TB/s, 2TB/s interconnect, Decode-optimized) represent chip-level phase specialization. The risk is that PR and DT resource ratios cannot be flexibly swapped as workload patterns change.
5. Software Ecosystem
Huawei's CANN community has 67 projects, >12M lines of open-source code, and 3,500 monthly active developers. H3C's software task is ensuring diverse hardware does not become multiple isolated systems. Dawning's strengths are in HPC long-duration job management.
III. Maturity Assessment (L1-L4)
| Level | Evidence Required | Enterprise Implication |
|---|---|---|
| L1: Architecture/Prototype | Protocol, chip, roadmap, demo unit | Track and research only |
| L2: Engineering Product | Full rack, cooling, software, system test | Enter POC |
| L3: Repeatable Commercial | Multi-customer, multi-batch, fault data | Core production candidate |
| L4: Token Economy | Auditable SLA, Goodput, cost data | Proven economics |
Key assessments: NVIDIA GB200/GB300 NVL72 at L3; Vera Rubin NVL72 at L2-L3; Kyber NVL144 at L1; Huawei CloudMatrix 384 at L3; Atlas 950 1,024-card at L2-L3; 8,192-card full config at L1-L2; H3C S80000 32/64 at L2; G-Link/1,024-card at L1-L2; Dawning scaleX640 at L1-L2; scaleX40 at L2 candidate.
IV. Scale Stratification
- 32–64 cards: Enterprise basic unit for RAG, LoRA, moderate inference
- 72–144 cards: Commercial main battlefield — significant Scale-Up benefits without uncontrollable fault domains
- 256–1,024 cards: Head models and core compute — conditional, requires proof of communication bottleneck
- Above 1,024 cards: Tiered Scale-Up and multi-cabinet optical interconnect
V. Enterprise Decision Framework
| Situation | Recommended Start |
|---|---|
| AI demand volatile, load varying | Public cloud or short-term rental |
| Stable inference, data sovereignty | Private mid-scale supernode |
| Sustained large-scale training | Build high-density Scale-Up system |
| XPU route undetermined | Open platform POC |
VI. Procurement POC Checklist
Required tests include: Time-to-Train, Token/s, TTFT, TPOT, P95/P99 latency; AllReduce/All-to-All bisection bandwidth and hot spot traffic; total rack input power and kWh per effective token; 7-day/30-day Goodput and job completion rate; fault injection for single card, switch board, link, optical module, CDU, and storage; Checkpoint and recovery time; model adaptation person-weeks and missing operators; reuse ratio of cabinets, networking, and software when switching XPU brands.
Test results should feed into:
Effective token cost = (3-year depreciation + facility modification + power/cooling + software licensing + operations labor + fault/replay losses + migration/exit costs) / (effective tokens meeting SLA)
VII. Conclusion
NVIDIA has the lowest delivery risk for CUDA-based, high-utilization workloads but requires accepting vendor lock-in and premium pricing.
Huawei is the closest domestic vendor to a complete operable system, covering chip, interconnect, software, server, and cloud. Its main challenge is keeping diverse models running at high utilization with low migration cost.
H3C offers the largest potential upside through lifecycle optionality — the ability to reuse cabinets, cooling, switching, and operations platforms when changing XPU generations.
Dawning has unique value for HPC, AI4S, and high-density systems engineering.
Enterprises should not pay for the largest card count announced at a launch event. They should pay for verifiable Goodput, controllable migration costs, maintainable electrical/mechanical systems, and clear upgrade paths.
Data cutoff: July 22, 2026. Not investment advice. Full Chinese version available.
[14 sources: NVIDIA Developer Blog ×3, arXiv CloudMatrix-Infer, Huawei Official ×2, H3C ×3, ZGC Group, Changsha Evening News, UALink 1.0, CXL Consortium, NVIDIA Blog]