Two things from November 2026 deserve to be read together.
The first comes from Astera Labs' Q3 earnings call. In the most heavily loaded systems, the company said, its fabric switching plus copper signal-conditioning products already bring in over $1,000 per XPU (accelerator); on the next platform, AI fabric products alone will be worth "well beyond $1,000 per XPU." Note who earns that money — scale-up switch silicon and signal conditioners: a company that sells no NICs is booking a thousand-plus dollars of networking silicon per accelerator.
The second comes from Broadcom: Thor Ultra — which Broadcom calls the industry's first 800G AI Ethernet NIC built to the UEC (Ultra Ethernet Consortium) specification — has been sampling since its October 2025 launch (commercial availability still unannounced), and together with Tomahawk 6 switches and Arista's 800G Etherlink forms the open camp's first complete network stack.
Both point to the same thing: the functions and budget of the network are being redistributed across three classes of devices. This is not a physical card being pried apart — the scale-up interface has always lived inside the accelerator package, and optical modules have always been separate parts. It is the job and value that the word "NIC" used to cover, now shared by three independently evolving devices — the SuperNIC that runs transport protocol state machines, the scale-up interface that exposes memory semantics, and the physical-layer parts that handle optical-electrical conversion and signal integrity. Three functions, three businesses, each with its own competitive landscape.
This article proceeds in four steps. First, the background: the decades of inertia in this component, and how AI workloads rewrote its feature list step by step. Then the mechanisms and the commercial status of each of the three devices as of November 2026. Finally, the judgments. We have deep-dived several of these battlefields separately — the open war in scale-up interconnects, the Broadcom-versus-NVIDIA networking silicon comparison, and Huawei's HC 2026 network panorama — so this piece pulls the lens back to the component itself: the card sitting next to the XPU, and what it is becoming.
1. A Porter for Decades, and the New Feature List AI Forced
The NIC spent decades as the least storied part of a server. From 10Mb Ethernet to 400G, its job barely changed: move packets in and out, and offload a few checksums for the CPU. It twice tried to get smarter. The first attempt was TOE (TCP Offload Engine) in the early 2000s, which moved protocol-stack processing from the CPU into the NIC — on the then-current judgment that general-purpose CPU performance was nearing its ceiling. The CPU did not hit a ceiling, and TOE failed: the iteration speed, ecosystem compatibility, and flexibility of general-purpose processors left dedicated offload logic unable to compete on value. The second attempt was the late-2010s SmartNIC/DPU: offloading "infrastructure work" — storage, virtualization, encryption — from the host CPU onto programmable silicon in the NIC. That wave stuck; its landmark was NVIDIA absorbing Mellanox for nearly $7 billion in 2020, taking both the InfiniBand private-network and the ConnectX NIC product lines, with AMD buying Pensando and Microsoft buying Fungible in tow.
But the DPU era's "intelligence" fundamentally worked for the CPU. What AI asks of the NIC is something else: manage the network's pathologies on behalf of the GPU. Two waves of workload drove that turn.
The first wave was training. The dominant communication in large-scale training is collective communication — hundreds or thousands of cards synchronizing gradients at every step. The NIC went from accessory to per-GPU fixture: in mainstream reference designs, one NIC per GPU (rail-optimized architecture), on a network that must be "lossless" — one dropped packet means one collective wait, and jitter in latency eats effective compute directly. InfiniBand owned this market first; to win it back for Ethernet, Meta, AMD, Microsoft, Broadcom, Arista and others founded the UEC in 2023, with the explicit goal of turning InfiniBand-grade determinism into an open standard on Ethernet.
The second wave is inference, and it rewrote the communication pattern itself. Today's frontier models are mostly MoE (mixture-of-experts); expert parallelism turned the dominant traffic from all-reduce into all-to-all: every routing layer sends tokens across the whole cluster to experts scattered across different cards — short messages, all-to-all, microsecond-scale completion, brutally sensitive to tail latency. Inference infrastructure has meanwhile converged on prefill-decode disaggregation: the pool that processes prompts is separate from the pool that generates tokens, and every served request requires one KV-cache transfer between them — a mass of short flows sitting directly on the critical path of time-to-first-token. The networking research community has started writing papers about exactly this: the NIAC (Networks for AI Computing) workshop at SIGCOMM 2026 featured a paper dedicated to routing collisions in KV-cache transfer (ARK; up to 34% lower P95 flow-completion time in its simulations). The application-layer evidence is just as direct: vLLM introduced push-based KV transfer in October, moving scheduling setup off the critical path — AWS's measurements on P5en showed time-to-first-token down to roughly a third of the original under heavy load (about a threefold improvement), with the two modes converging under light load — and the precondition is GPUDirect RDMA (writing straight into GPU memory, bypassing the CPU).
Why couldn't the old NIC absorb this? The legacy Ethernet trio each carries a mine. ECMP (equal-cost multi-path) hashes per flow, but AI traffic is dozens of elephant flows firing simultaneously; one hash collision produces a hotspot — by NVIDIA's account, standard Ethernet delivers only about 60% effective utilization under AI load. PFC (priority flow control) prevents drops by having the receiver pause the sender, which propagates congestion backwards along the path and drags innocent flows into the blast. DCQCN (explicit congestion notification-based control) converges slowly — published figures range from hundreds of microseconds to tens of milliseconds — too slow for microsecond-scale all-to-all. These three mines set the direction of every new feature that follows: not patches, but replaced mechanisms — even the meaning of "lossless" is being redefined along the way.
2. The First Device: The SuperNIC, Managing Four Uncertainties
The industry has already named the new NIC on the scale-out side (the network across racks and pods): the SuperNIC. It is best summarized as a dedicated computer that runs transport protocol state machines, tasked with managing four uncertainties on behalf of the GPU.
Path uncertainty — packet spraying, plus delivery without reordering. Legacy ECMP routes per flow; the new mechanism routes per packet: one flow's packets spread across all equal-cost paths, leaving hotspots nowhere to form — the 60%-to-95% utilization gap above is served mostly by this (95% is NVIDIA's figure for the full Spectrum-X stack). The price is heavy reordering at the receiver, so delivery semantics had to be redone. The UEC specification defines a family of delivery semantics, represented by RUD (reliable unordered delivery): each packet carries its own offset, the receiver acknowledges on write, and no reorder buffer is required. For classic RDMA (in reliable-connection mode), the delivery semantics require ordered landing — the reorder buffer is a double amplifier of latency and memory; hand "ordering" up the stack (collective libraries are naturally order-agnostic) and that amplifier disappears.
Congestion uncertainty — NIC-switch coordinated congestion control. Incast (many-to-one) is all-to-all's congenital disease. UEC 1.0 defines a dual-sided mechanism: sender-side congestion control (NSCC) adjusts rates at sub-RTT speed based on round-trip time and explicit congestion markings; the receiver side (RCCC) is essentially credit authorization — the receiver converts available buffer into credits and feeds them back, the sender transmits only with credit in hand, and congestion is gated at the source. The two can run individually or together. NVIDIA's proprietary implementation runs the same direction: switches broadcast congestion telemetry to the NICs, and senders slow down before buffers overflow — in the official phrasing, "the drop never happens." The shared point: "lossless" has turned from a switch-buffer technique into a joint protocol between NIC and switch.
Neighbor uncertainty — performance isolation. In multi-tenant fleets, "your neighbor's training eats your inference bandwidth" is solved by two-level fairness: per-tenant shaping at the NIC, per-queue scheduling at the switch. In inference clouds this is a purchase reason, not an option.
Trust uncertainty — per-packet transport-layer security. UEC writes "security as a first-class citizen, co-designed with the transport" into the specification, landing as per-packet authenticated encryption (the PSP protocol family): each packet is verified independently, with no dependence on per-flow path state — which is exactly what makes it compatible with spraying, since every packet may take a different path.
Two new duties join the list. First, in-network collectives: a deployed ring AllReduce already runs at O(N) total traffic — each node uploads and receives one copy — but it serializes 2(N−1) hops; with the switch adding packets in flight, each node uploads one copy and receives one aggregate, collapsing multi-hop serialization into a single hop. Traffic is the same order; steps and latency fall sharply — which is precisely what tail-latency-sensitive workloads buy. The idea dates to InfiniBand's SHARP and is now written into the UEC specification and Broadcom's Tomahawk Ultra switch silicon. Second, connection management for short flows: in the spirit of TLS 1.3 zero-RTT, data flows before the handshake completes and idle connections are torn down at zero cost — built for the mass of per-request KV-cache transfers.
Commercial snapshot (November 2026). NVIDIA's proprietary stack is the most mature: the 800G ConnectX-8 (dual-protocol InfiniBand/Ethernet, PCIe Gen 6) is the current workhorse, and the Rubin generation moves to the 1.6T ConnectX-9 per NVIDIA; the NICs pair with Spectrum-X switches as the "adaptive routing + telemetry-based congestion control + performance isolation" trio, with xAI's 100,000-GPU Colossus as the flagship case — all per NVIDIA. The open camp is just starting: UEC 1.0 was published in June 2025, currently at 1.0.3 (July 2026), covering the full stack from software to physical layer — NICs, switches, optics, cables all specified — with more than a hundred members; Broadcom's Thor Ultra has sampled for over a year (commercial availability unannounced), Arista's 800G Etherlink is shipping, and the cloud self-designed line (AWS's EFA and peers) is deployed at scale. The structural point: UEC has turned the capability NVIDIA monetized through proprietary NIC-switch co-design into a purchasable open specification — Ethernet merchant NICs get, for the first time, the full arsenal to compete head-on with the proprietary stack — last time out, RoCE only got half.
3. The Second Device: The Memory-Semantic Interface, Stretching the Memory Bus
On the scale-up side — within a rack or supernode, stitching many XPUs into one large machine — the "NIC" stops resembling a NIC altogether. It does not carry messages; it extends memory. Three mechanisms define the device.
One-sided memory semantics. Message semantics (send/receive) is a two-sided operation: software on both ends participates. Load/store is one-sided: the initiator reads or writes a remote address directly, while the remote CPU and GPU never participate. The precondition is unified addressing: Huawei's UnifiedBus (Lingqu) interconnect addresses a 1,024-card domain as one 256 TB address space (a pooled unified-addressing figure; installed memory is 147 TB), and NVIDIA's NVLink builds a coherence domain — model shards in remote HBM are accessed like local pointers.
Bandwidth matched to the collective. Per-card bandwidth here is 1.8–3.6 TB/s — from the current NVL72 to the coming NVLink 6 (3.6 TB/s per package), with UnifiedBus 950 at 2 TB/s per card — roughly twenty to thirty-plus times today's 800G scale-out NIC (about 100 GB/s), and still about an order of magnitude above the Rubin generation's 1.6T NIC (about 200 GB/s). The reason is economics: collective communication runs inside the domain at every step, so domain bandwidth multiplies straight into effective compute. The account has two layers. One is capacity and latency: a 1,024-card supernode carries 147 TB of installed memory, holding dozens of FP8-quantized MoE weight copies of the V4 class (~2 TB each, by our estimate), with expert-parallel all-to-all kept entirely inside a domain of roughly 3 microseconds round-trip. The other layer is organizational gain, in the terms of Huawei's Markov laboratory simulation: the same 100,000 cards, organized as 4,096-card supernodes rather than 8-card servers, lifts MFU by 2.75 times — against the reference frame of traditional architectures losing more than forty percent of training time to communication. Domain size converts directly into money.
Reliability guaranteed by the link, not end-to-end retransmission. Credit-based flow control — the receiver grants, the sender transmits only with credit — keeps packets from queuing inside switches, so link latency converges to propagation plus forwarding: by Broadcom's account, Tomahawk Ultra's forwarding latency is 250 nanoseconds at full 51.2T throughput; link-level checking and retry cover the rest. Short links with controlled error rates need no end-to-end transport retransmission state machine.
Race snapshot. We have deep-dived this battlefield ("NVLink's Moat and Its Cracks"); here are three updated checkpoints. First, NVIDIA opened NVLink as the Fusion licensing ecosystem in May 2025 — the first time a proprietary bus dealt cards to outsiders; Marvell expanded the partnership in March 2026 to build Fusion-compatible custom XPUs and scale-up connectivity, with NVIDIA taking a roughly $2 billion stake in Marvell and the cooperation extending into silicon photonics. Second, UALink (an open standard initiated by AMD and governed by a nine-company board) is moving from specification to silicon: multi-vendor demonstrations on the 1.0 spec have appeared, and in April 2026 it published 2.0 plus companion specifications (in-network compute, chiplet interfaces, manageability, 200G performance); Astera's 320-lane Scorpio X switch silicon is shipping to hyperscalers with a production ramp in the second half of 2026 (per the official release; it currently runs Astera's own memory-semantic fabric), while Marvell's native UALink switch is slated for 2027. Third, the Ethernet camp's third path: Broadcom contributed its SUE-T transport specification to OCP's ESUN (Ethernet scale-up networking) workstream, running scale-up over Ethernet framing so one Ethernet ecosystem serves both markets. China is an independent fourth path: the UnifiedBus protocol is open-sourced, and the SF9300 dual-mode switch announced at HC 2026 supports dual RoCE/UnifiedBus networking (per Huawei: existing RoCE NICs can gain UnifiedBus capability, with the value realized mainly inside the supernode boundary) — a different road from the West's "must-swap-in smart NICs": the compatibility layer lives in the switch.
Three new shapes are worth recording. Scale-up is turning from proprietary bus into purchasable ecosystem, with the 2026–2027 window commoditizing all three routes (licensing, open standard, Ethernet retrofit). UALink 2.0 writes chiplet interfaces into the standard, extending the same memory semantics from rack scale down to inter-package. And a PCIe middle form has appeared: Astera's Orion uses PCIe switching to build inference pods of 8 to 160 cards (company figures) — keep your protocol, get the big domain first; the pragmatic choice for inference customers.
4. The Third Device: The Photonics Physical Layer — the DSP's Electric Bill and Copper's Limits
The third class of devices looks least like a "NIC," yet is eating the biggest slice of the NIC budget: optical-electrical conversion and signal integrity.
Start with the DSP's electric bill. In pluggable optical modules, the DSP (retiming chip) is the largest single consumer: 16–17 W for an 800G module (three vendors' figures agree), and 20–25 W for next-generation modules by NVIDIA's account. A 64-port 51.2T switch burns over a kilowatt on optics alone, before the switch ASIC itself counts. AI clusters run thousands of optical links; "the electric bill of light" has moved from the network budget into the rack power budget — every watt saved on optics is a watt available for compute.
The industry's answer runs along two fronts. On the host side: LPO (linear pluggable optics) removes the DSP from the module entirely, letting the host-side SerDes drive the optics linearly — power nearly halves (800G drops from about 16 W to around 8 W), and the DSP's processing latency goes with it. The cost: the link becomes a co-designed system — host, channel, and module must jointly fit the signal budget, interoperability must be validated pairwise, and reach stays short; LRO is the compromise, keeping the DSP on transmit and going linear on receive. On the switch side: CPO (co-packaged optics) puts the optical engine in the same package as the switch ASIC, shrinking the electrical path from tens of centimeters to a few millimeters — the signal arrives intact, and the DSP layer disappears entirely. Per NVIDIA's account (NVIDIA/Lambda press release): 3.5x power efficiency, 10x resiliency, 5x sustained application runtime; on optical power specifically, NVIDIA technical briefings claim up to 5x savings for scale-out. The long-criticized maintainability problem now has an engineering answer: the lasers stay on the faceplate, hot-swappable. One notch less radical on the same front is NPO (near-package optics): the optical engine sits on the substrate rather than in the package — Huawei's Ascend 960 supernode uses 5,500 Hi-ONE optical engines to replace 48,000 800G pluggables, a reduction to about one-ninth, itself a precondition for a 4,096-card domain to exist.
Copper is approaching its limit from the other side. Signal rates double each generation, and unretimed copper reach halves; at 224G, copper reaches roughly a meter inside the rack. A product category that did not exist before has emerged around this: the choice between redrivers (analog amplification and equalization — cheap, low-power, but no eye reconstruction) and retimers (clock-data recovery — thorough, but power-hungry) used to be a one-time design decision; Astera's Taurus line puts the two in one standard OCP footprint — swappable at any design stage without a board redesign. Its existence is itself a declaration: wherever copper still reaches, the industry's choice is not "switch to optics" but "build the scale-up domain as a backplane."
Commercial snapshot. NVIDIA's Quantum-X Photonics (InfiniBand, 144×800G = 115.2 Tb/s as announced; the commercial SKU is 72 ports at 1.6T with the same total) is shipping, with Lambda among the first to deploy; Spectrum-X Photonics SN6800 (Ethernet, 512×800G = 409.6 Tb/s) was originally slated for late 2026 and now sits at the delivery-decision point. Broadcom's third-generation co-packaged switch, TH6-Davisson, was shown at OCP 2026, aimed squarely at the rack-power wall. The LPO camp has production parts. Where this layer's "standard" lives is worth noting: not in committees, but at the foundry — NVIDIA's official account says co-developed "with partners like TSMC"; supply-chain accounts point to TSMC's COUPE silicon-photonics platform as the foundation. The supply chain is dividing accordingly: module vendors retreat from "selling whole modules" to "supplying optical engines and lasers," with value shifting toward switch-silicon vendors and foundries.
5. Judgments
First: the NIC as a single product category is failing, and networking value is dividing into three businesses. The one that sells tail latency (SuperNIC), the one that sells domain size (memory-semantic interface), and the one that sells energy per bit (photonics physical layer) — NVIDIA and Broadcom field products in all three, but in each market they face different opponents on different scoreboards. Astera's thousand-plus dollars per XPU lands almost entirely on scale-up switching and signal conditioning, barely touching the NIC — evidence that networking-silicon value is leaving the NIC for the three device classes. Procurement language, vendor landscapes, and the very word "NIC" will be rewritten along with it. The failure conditions of this judgment are equally clear: if platform vendors pull the three devices back into a single package, or UEC commercialization fails and open specifications recede, "splitting" becomes "re-integration."
Second: the two hidden lines deserve more attention than the visible ones. One: the two networks are stealing each other's moves — scale-up took in-network compute (written into UALink 2.0), scale-out took credit-based flow control (RCCC is credit authorization in essence); divergence and convergence are happening at once, and the boundary will keep moving. Two: the form of "openness" itself is changing — protocol-layer standardization is returning to committees (UEC, UALink), while physical-layer standardization is returning to foundries (COUPE); the former dismantles proprietary walls, the latter turns "open" into "anyone can tape out."
Third: China and the West weight their NIC-switch coordination differently, each fit for its own context. The Western camp also puts plenty of intelligence into switches (SHARP, Tomahawk Ultra's in-network aggregation, Spectrum-X telemetry), but its designs require a SuperNIC at every endpoint — full performance means replacing the NICs; Huawei puts the compatibility layer into the switch (SF9300 dual-mode networking — per Huawei, existing RoCE NICs gain UnifiedBus capability via upgrade, with value realized inside the supernode boundary), so NICs can stay, at lower installed-base cost. The domain-scale collision is more direct: the Western flagship in production is a 72–144-card NVL domain, with Rubin Ultra's NVL576 slated for 2027; Ascend's commercial delivery units start at 1,024 cards (950, 2026) with 4,096 in progress (960, 2027), and the full SuperPoD roadmap tops out at 8,192/15,488 cards (HC 2025 roadmap figures) — the domain-economics account ("forty percent of communication time traded for 2.75 times effective compute") is the scoreboard of that collision.
The verification points stand here: actual 2027 shipments of UEC commercial NICs; who becomes the open ecosystem's first marquee customer once native UALink switches land; actual Spectrum-X Photonics SN6800 deliveries from late 2026 into early 2027; whether the UnifiedBus dual-mode switch finds customers outside Huawei's ecosystem; and CPO's share of new AI ports in 2027. Any one of these five resolving — either way — updates the judgments above.
Related reading
- "NVLink's Moat: The Battle for Open Scale-Up Interconnect"
- "Broadcom Tomahawk 6 vs NVIDIA Networking Chips: A Full-Stack Benchmark from Silicon to AI Factory"
- "Huawei's One Network: The HC 2026 Networking Panorama"
Sources
- Ultra Ethernet Consortium: Specification 1.0 release and specification pages (published 2025-06; current 1.0.3, 2026-07-16; consortium founded 2023-07-19 with nine founding members); Inside Deep Tech, "Ultra Ethernet: A Full Guide to AI Scale-Out Fabric" (NSCC/RCCC, profile layering, 2026-09)
- Broadcom: Thor Ultra launch release (2025-10-14, sampling); company newsroom (TH6-Davisson, SUE-T/ESUN, OCP Global Summit 2026)
- Astera Labs Q3 2026 earnings call (verbatim: "next-generation AI fabric products alone … well beyond $1,000 per XPU"; current-gen fabric switching + copper signal conditioning already above $1,000 combined); Astera official releases (2026-05-05, Scorpio X shipping, 2H26 ramp; 2026-07-21, Taurus OCP-footprint Smart Swap); UALink Consortium (2026-04-07, spec 2.0 plus four companion specifications); NextGenInfra, "2026 AI Infra Summit" notes (UALink demos, 2.0/3.0)
- Marvell × NVIDIA: expanded partnership, March 2026 (Fusion-compatible custom XPUs, scale-up connectivity) and roughly $2B investment (multiple sources: StockTitan, Converge Digest, Yahoo Finance)
- NVIDIA/Lambda: Quantum-X Photonics commercial availability and first deployments (3.5x efficiency / 10x resiliency / 5x sustained application runtime, vendor figures); ConnectX-9 (1.6T) pairing with the Rubin generation per NVIDIA GTC 2026 materials; NVIDIA technical briefing (up to 5x scale-out optical power savings, SN6800 409.6 Tb/s, 20–25 W pluggables)
- LPO/LRO power figures: Vitex, Axiom, AscentOptics, FS (800G DSP 16–17 W; LPO 8–8.5 W)
- vLLM, "Push-Based KV Transfer" (2026-10-14) and the AWS ML blog measurements (P5en, up to 3x TTFT under heavy load; TechTimes and others as secondary); TensorRT-LLM disaggregated serving documentation; ARK, arXiv:2610.41160 (SIGCOMM 2026; P95 figure from the paper abstract)
- xAI Colossus scale and Spectrum-X 60%→95% utilization are NVIDIA figures (2024-10-28 release)
- Domain economics and UnifiedBus/Ascend data: our verified technical notes (Ascend 960 supernode, HC 2026 networking, DeepSeek-on-Ascend cluster analyses); the 2.75x figure is Huawei Markov laboratory simulation; Huawei's HC 2025 Xu Zhijun keynote (Atlas 950 SuperPoD full configuration 8,192 cards; Atlas 960 SuperPoD 15,488) and WAIC 2026 (1,024-card commercial unit) coexist as two official framings; NVLink 6 at 3.6 TB/s from our published Rubin-series verification