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Thinking
Long-form notes for reading the direction of technical change.
Thinking is a professional column: fewer quick posts, more durable essays. It keeps observations, source trails, assumptions, and evolving viewpoints visible over time.
Essays
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September 2026
17 essaysDeepSeek DSec: Training Infrastructure Serving About 3 Million Sandboxes a Day
DeepSeek’s DSec serves about 3 million sandboxes a day, letting agents run training tasks in real environments. This article unpacks how it uses independent environment layers and on-demand reads to cut preparation overhead, memory sharing and reclamation with CPU scheduling to carry large numbers of concurrent sessions, and decoupling from preemptible GPU training to preserve execution progress. Public experiments verify the gains of some mechanisms, but they are not yet enough to fix the ratio between environment and GPUs. Judging such platforms also depends on the supply of valid training trajectories, recovery overhead, and total cost.
Yunqi 2026: Alibaba’s Chip-Model-Cloud Full Stack
Yunqi 2026 put three releases on one stage: Zhenwu V900 (3× per generation, 216GB, 2027Q1), Qwen’s zero-human RSI loop (33 rounds, AA 40→45), and a cloud rebuilt for agents (AI storage cost −69%, a 20GW target). This piece reads each in turn — how real the “3×” is against Ascend 960 and NVIDIA B300, where RSI’s boundaries sit, and why the unit of competition has moved from the single chip to the whole system.
HC 2026 Panorama: The Unit of Competition Shifts from Chip to System
A panorama read of Huawei Connect 2026: six components, from intelligent-computing supernodes and general-purpose supernodes to memory storage, interconnect, cloud services, and industry portfolios, stacked into one system diagram. The piece draws the commercial status line first (buyable, deploying, or calendar), then unpacks the two compute legs, the four cluster numbers and one verification chain, how the M900 writes storage into the execution path, and delivery as combinations across cloud and industry. The conclusion: a system, not a catalog, and the unit of competition is shifting from single products to whole systems.
UnifiedBus 2.1: Compute Interconnect Sets Its Own Pace
One day after Huawei Connect 2026 opened, the 586-page UnifiedBus Base Specification 2.1 landed: three new rate tiers, reliable reroute, fused-write transactions, 24-bit CNA — 12 categories of revision. The same forum also delivered a compatibility test spec and the first third-party silicon timeline. This piece takes apart 2.1 against 2.0 and reads two signals: the compute interconnect has started setting its own rate cadence, and the UnifiedBus ecosystem now has a timeline for stepping outside Huawei’s walls.
Zhipu's ZCode “Silent Upload” Incident: A Review and Analysis
Zhipu's ZCode was caught silently uploading entire Git histories: 86.6% of a 313MB pending archive was Git history, and only the vendor held the key to the envelope encryption. This review reconstructs the September 16–21 timeline and the upload pipeline, checks what remains after remediation, open-sourcing and third-party audits, unpacks why the community rejected the “docs generation” explanation, and offers an actionable checklist for regulators, enterprises and developers.
Huawei’s One Network: The HC 2026 Networking Panorama
Huawei’s HC 2026 networking launches, mapped onto the five-network coordinate system from our Hot Chips 2026 coverage: four of the five answered, all on one Lingqu UnifiedBus stack. The piece walks the scale-up bus domain from rack to floor, the two-tier multi-plane cutting cost and latency at once, why Huawei ships no DPU, the AI context plane as the new battleground, the four lines of light, and a registry holding exactly one vendor. Three judgments close: four networks on one stack, context as the 2027 deciding point, and governance deciding the ceiling.
The Model Optimizes the System, the System Runs the Model: Building GLM's Frontier Inference on 100,000 Domestic Accelerators
All production inference for GLM-5.3-Flash runs on more than 100,000 domestic AI accelerators. A teardown of the foundation, feedback engineering, and engineering loop that took it from first run to full traffic in under two weeks—and how 3× efficiency became 1/40 the price.
Same Node, Double the Compute: How Ascend 960 Rebuilds the Chip, the Supernode, and the Cluster
With the process node pinned at N+2, Ascend 960 doubles compute through three system-level levers: chiplet packaging and in-house HBM at the card level, a 4,096-card supernode whose 5,500 NPO optical engines replace 48,000 pluggable modules, and cluster topology that fences communication inside a 2-microsecond latency domain. Set half a generation off from Rubin Ultra in 2027, the domestic inference cost curve is starting to decouple from GPU pricing.
Fitting a Trillion Parameters into One Machine: HBF and the Three Knobs of Memory Provisioning
A September Huawei paper offers a configuration answer for single-node trillion-parameter appliances: weights in HBF, the state tier on commodity LPCAMM2 modules, and one quarter of internal bandwidth exposed to the host. The article verifies the knees of three independent budget lines and maps the debate between OXMIQ and five academic papers; the criticism axes differ, but on weights belonging in HBF the verdict is unanimous, and both camps marked the same land on the map.
Folding Makes the Chip Run Cooler: Reading Huawei's τ-Law V3 Paper Against the Kirin 9050 Pro Measurements
Logic folding lifts transistor density by 55 percent, and the instinct says the chip should run hotter and burn more power. Huawei's third τ-law paper, titled "Huawei's τ Chip Was Supposed to Melt?", answers head-on: in large AI clusters more than 80 percent of energy goes to data movement, and smartphone SoCs show the same imbalance to a milder degree, so folding shortens wires and spends a doubled transistor budget on voltage, cutting NPU (neural processing unit) power 66 percent at equal performance. This essay unfolds the paper’s full argument — the two energy accounts, power falling with the square of the supply voltage, the redirection of the thermal argument — and audits it line by line against Geekerwan’s Mate XT2 measurements: three fits (single-core gain almost exactly equal to the frequency gain; the multi-core efficiency curve in the same tier as the Dimensity 9400; NPU measured 67.7 against the paper’s 70 TOPS (trillion operations per second)) and one gap (the launch event’s 142 percent versus the paper’s 42), with three judgments and the dates that will decide them.
The Two-Trillion-Dollar Circular Ledger: Anthropic's IPO and the First Public Reckoning of AI Capital
The outline of the largest IPO in history is complete: Nvidia is in talks to anchor up to $10 billion as Anthropic seeks to raise $100 billion at a $2 trillion valuation, past the records SpaceX set in June. This editorial lays the past ten months of circular contracts into a ledger: behind every equity investment sits a larger compute-procurement commitment, and the money comes back once through infrastructure bills, again through equity appreciation. With SpaceX’s prospectus as the control group, three judgments: the listing documents will lay the ledger open for the first time; what this IPO prices is capital-expenditure endurance; governance and the safety narrative become the balance-sheet entries.
Marvell Is Betting on Everything Between the XPUs: Optical Interconnect, a Memory Fabric, and a 97.7% Performance-Vested Warrant
The AI infrastructure bottleneck narrative has migrated from compute to data movement. What Marvell brings to the AI Infra Summit is three product lines, a $3.25B Celestial AI acquisition, a CXL interop milestone with NVIDIA Vera, and a Google warrant that vests 97.7% on purchases. This piece takes the board apart: how interconnect turned from accessory into catalog, how the memory war moved between racks, and why the wager is replacing the promise as the grammar of AI capital.
From Blueprints to 100,000 GPUs: Matryoshka, Meta's Network Compiler
How does a network design blueprint become configuration running on thousands of switches? Matryoshka, published at NSDI '26, turns that delivery step into a compiler: six years in production inside Meta, 400 thousand lines of code, supporting nearly 900 datacenter networks, with its latest work the 100K-GPU supercluster that carries LLaMA training. This article takes its operation apart: the seven-stage pipeline, stateless recompilation, two-stage validation, and a production scorecard.
Microsoft Moved "Yield" into AI Infrastructure: Maia 200 and the Yield-Defined Architecture
Microsoft's September 1 blog shipped no product; it proposed a new yardstick for AI infrastructure: yield. This analysis reads the Maia 200 inference platform together with that manifesto: how the FP4-first datapath, two SRAM tiers with three-level DMA, and the FCQ + ATL two-tier scale-up topology make useful tokens per dollar and per watt the design objective, closing with three judgments and three verifiable nodes.
AI Cluster Observability Series: How Meta's RDMATracer Closes the Kernel Blind Spot with 13 eBPF Probes
A deep dive into Meta's NAIC '26 RDMATracer paper: 13 curated eBPF probes on RDMA control-path kernel functions, emitting only on failure, light up a blind spot where 96% of syscall failures carry no accompanying signal, at 0.0000024% of one CPU per host.
Looped Transformers Hit the Frontline: Why OpenAI, Zhipu, and Academia Converged on the Same Stack of Layers
Recurrent depth turns model depth from an architectural constant into a runtime variable. This piece traces the route's seven-year lineage and engineering boundaries: Huginn made the case, Nanbeige proved it in production, and Astra and Zhipu carried it into the frontier narrative. The limits of the gains, and the cost in monitorability, are equally clear.
MetaRoCE in Depth: RDMA Designed for Loss, an Open Standard for Million-GPU Scale
MetaRoCE is Meta's clean-sheet RDMA transport protocol, opened through OCP. This analysis works through six questions: why it appeared, what it actually is, why Meta opened it, how the protocol works inside, what it is worth and to whom, and a closing peer review of ByteDance MegaScale, Alibaba HPN, Tencent Xingmai, AWS SRD, Google Falcon, and the UEC/MRC alliances.