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Thinking
Long-form notes for reading the direction of technical change.
Thinking is a professional column: fewer quick posts, more durable essays. It keeps observations, source trails, assumptions, and evolving viewpoints visible over time.
Essays
35 essays shownAugust 2026
35 essaysThe Token Factory Ledger: Inference Economics in SiliconFlow's Prospectus
Revenue of RMB 55.3M in 2025 (+653%), gross margin of -24%, net loss of RMB 345M, valuation of RMB 7.74B — SiliconFlow took its “Token Factory” story to the Hong Kong Stock…
2026Q2 NVIDIA Earnings: From Selling Chips to Selling AI Factories
Revenue of $96.2B, guidance above $100B for the first time. The evidence that NVIDIA is converting "selling chips" into "selling AI factories" is now complete. Four layers:…
Agents Pull the CPU Back to the Table: Four Questions from Hot Chips 2026
Six Hot Chips 2026 CPU talks distilled into four questions: the serial bottleneck (Vera's wide front end vs IBM's 5.7GHz), the memory power budget (SOCAMM2's 30-40W full load vs…
Five Networks for the AI Factory: Spectrum-X Multi-Plane and the 512K-GPU Scale
Spectrum-X multi-plane splits the AI factory network into five dedicated planes, scaling 64× to 512K GPUs via 8 planes by 4 rails. CPO reaches volume production: 4× fewer lasers,…
Hyperscaler Silicon, Generation Two: Three Routes to the Training–Inference Split
Three clouds all brought second-generation custom silicon: MTIA 400's dual mandate (with MTIA 300, the first DLRM training chip, now measured), MAIA 200 carrying GPT-5.2 on SDLA…
Intel's Triple Launch: 18A Full In-House, 350W Air-Cooled Inference, UCIe Open Packaging
Three Intel talks form a complete deployment-cost logic chain: Diamond Rapids for rack orchestration with Foveros Direct 3D, Crescent Island sidestepping HBM with 480GB LPDDR5X…
Four Routes Against the Memory Wall: Hot Chips 2026 Delivers the Answer from the Silicon Side
Micron sizes the wall with four bills: about 90% of package area to memory, roughly 3x the wafers for equal capacity, and 17% of training interruptions tied to HBM. Samsung…
Hot Chips 2026 Overview: Per-Token Economics Is Forcing Decode Specialization
Twenty-seven talks across two days, collected into one map and inventoried by four directions: the CPU orchestration layer, the memory wall, five accelerator routes on decode…
OpenAI Turns In Its Scorecard: An Analysis of the First Measured Results for Its In-House Jalapeño Chip
At Hot Chips, OpenAI delivered Jalapeño's first measured results: 1.5-1.9× the per-watt throughput of Blackwell systems across three models, 1.7-3.6× lower latency. A reckoning…
Dissecting SemiAnalysis AgentX: The First Big Exam for Agentic-Era Inference
SemiAnalysis spent $3M capturing real Claude Code traces, open-sourced 393 sessions, and measured agentic inference across 1,000+ chips. This piece dissects AgentX 1.0 layer by…
From Solo Bet to Consensus: Groq 3 LPX Full Production and Low-Latency Inference's Eight Months
Eight months ago, folding an inference-chip company into its platform was NVIDIA's solo bet; eight months later it became six companies' default architecture. This piece grades…
Protocol Stacks at 1.6T Ports: The Kernel Stack's Last Mile and Four Ways Out
As ports head to 1.6Tbps, the protocol-stack CPU tax becomes a cost line the size of bandwidth itself. Seven papers, four routes: Presto's full TCP state machine in a switch…
The Photonic P4 Moment Hasn't Arrived, but the Language Has: lambda-lambda and the Photonic Software Stack
SIGCOMM 2026's Best Paper went to a programming language: lambda-lambda encodes optical physics in linear types (light cannot be copied = use exactly once), rejects unrealizable…
Collectives Become a Runtime: SIGCOMM 2026's Collective-Communication Turning Point
Three production realities — MoE explosion, superpod heterogeneity, multi-tenant fairness — are turning collective libraries into runtime systems. Fifteen papers, five routes:…
Scale-Up Is the New Datacenter Network: SIGCOMM 2026 Re-runs 2015-2020
NVL72 and CloudMatrix384 production volumes turned the intra-rack interconnect into a real network: measurement first, a topology cost revolution (Huawei BST at half the cost),…
KV Cache Becomes a Network Citizen: How SIGCOMM 2026 Rewired LLM Inference as a Networking Problem
After PD disaggregation, KV cache became explicit network payload. Six papers across five layers: runtime compression policy, idle video-codec ASICs, dual-path loading, endpoint…
SIGCOMM 2026 Close Reading: The Networking Community Moves Its Coordinate System onto AI Infrastructure
A session-by-session count of 110 SIGCOMM 2026 papers: AI-workload papers at 27%, three of nine workshops directly on AI interconnects. Five threads, five structural judgments,…
The SubQ Three-Month Audit: The Technology Is Real, the Narrative Ran Ahead
On May 5, Subquadratic released a model, SubQ, claiming a 12-million-token context window and attention computation cut nearly a thousandfold versus dense architectures. The most-c
The Toll Booth, Bought Out: When Intelligence Flows Through Stripe's Pipes
Stripe acquires OpenRouter for $7.5 billion: a 5.8x valuation jump in 82 days. The routing layer proved middle-layer value can be captured, then the payments layer bought it…
The Eighth Consumer: A Review-Gated Learning Loop for the Agent Harness
The event log already has seven classes of consumers—six at runtime plus snapshot replay at test time—everything except a learner. This piece lays out a build-ready reference…
Laws Before Code: DeepSeek Harness and Composability-First Design
A theory-first distillation of composability: one meta-constraint, eight dimensions, twelve design theses, five families of portable laws. DSH does not shrink the composition…
A Generational Upgrade Without a New Engine: GLM-5.3 and the Second Half of Post-Training
GLM-5.3 ships on the exact same 743B base as GLM-5.2, with every gain from post-training: Terminal-Bench up six-fold, coding near Fable 5, CyberGym past Mythos 5 as the best…
DeepSeek Harness Architecture Design Analysis: When 'Everything Is a Plugin' Goes from Slogan to Source Code
Source-code-level architecture analysis. Nine architectural decisions point to one verdict: DSH is building an agent operating system layer. But this OS can only execute, not…
DeepSeek Harness and China's Big Six Agent Harness Landscape
Six vendors, three routes: DSH's architecture reconstructed within China's Agent Harness landscape. Written on the eve of the August 13 open-sourcing, with a post-open-source…
Agent Storage Paradigm Reassessment: After FMS 2026, Projections Became Products
About a month later, the four-stage framework is validated and revised with FMS 2026 products. Stages 3 and 4 happen simultaneously. Bus dimension deep-dive: three new paths from…
FMS 2026: The Storage Hierarchy Is Being Networked
AI is transforming the storage hierarchy from discrete layers into a shared, schedulable resource network. FMS 2026 analyzed across three dimensions: bus technology (UCIe/CXL…
Can a Harness Evolve Itself?
A 9B model, weights frozen, nothing changed but the runtime logic — success rate jumped 9.3 percentage points. Harness-R1 is the first to turn harness modification from a manual…
KV Cache Scheduling Engineering: After Compressing to 7%
V4 Flash CSA+HCA architecture-level hot-cold tiering, strategy benchmarks, end-to-end 8×H100 case study, delta encoding outlook. FMS 2026 hardware validation added.
The Efficiency Limit of Model Memory: From MLA to CSA+HCA
First understand Tang et al. three-axis taxonomy, then test against production reality. V4 abandons MLA, KDA and Gated DeltaNet reach production.
Inference Pricing Teardown: The Physical Cost of a Token
Reverse-engineering inference pricing from V4 Flash/Pro dual-model pricing, 70%/83% margin cross-validation. FMS 2026 data added — memory at 50% of system value.
When Agents Learn to Remember: Meta Muse Code's Runtime Philosophy
Meta releases Muse Code, its first AI coding agent. Performance isn't the strongest, but three runtime architecture choices — persistent background agents, event-log-driven crash…
The Model Is the Computer: Why AMD Bought Taalas
Taalas etches model weights directly into mask ROM silicon, eliminating HBM dependency and achieving 48x GPU inference speed. AMD likely positions it as a decode accelerator in…
Two Paths: Kimi K3 vs DeepSeek V4 Architecture Divergence
K3 and DSV4 pursue different extremes from MLA. Intelligence: occasional precision vs consistent semi-precision. Engineering: five-step deployment derivation. Judy final review…
The Google AI Earthquake: When Research Leaders Exit and Engineering Delivery Takes Over
Hassabis steps down as DeepMind CEO, Jeff Dean leaves after 27 years, the CEO position disappears. Google AI reshuffle signals a paradigm shift from research-driven to…
Physical Constraints in the AI Supply Chain: Four Bottlenecks and the Reshaping Landscape
Nine major CSPs 2026 capex reaches 886.7 billion USD, 1.5x global chip output. But CoWoS effective output is falling, HBM has shifted to rationing, and the Texas grid has frozen…